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publication number s71jlxxxhxx_00 revision a amendment 3 issue date may 25, 2004 preliminary distinctive characteristics mcp features ? operating voltage range of 2.7 to 3.3 v ? high performance ? access time as fast as 55 ns ? packages ? 73-ball fbga?8 x 11.6 mm ? 88-ball fbga?8 x 11.6 mm ? operating temperatures ? wireless: ?25c to +85c ? industrial: ?40c to +85c general description the s71jlxxxh series is a product line of stacked multi-chip products (mcp) and consists of ? one or more s29jl064h flash devices ? sram or psram options ?8mb x 8/x 16 sram ? 16mb x 16-only sram ? psram x 16 only: 8mb psram 16mb psram 32mb psram 64mb psram the products covered by this document are listed below. for details about their specifications, please refer to the individual constituent data sheets for further details. mcp number of s29jl064h to t a l f l a s h d e n s i t y sram/psram density s71jl064h80 1 64mb 8mb s71jl064ha0 1 64mb 16mb s71jl064hb0 1 64mb 32mb s71jl128hb0 2 128mb 32mb s71jl128hc0 2 128mb 64mb notes: 1. this mcp is only guaranteed to operate @ 2.7 - 3.3 v regardless of component operating ranges. 2. byte# operation is only supported on the s71jl064h80xx0x. s71jl128hc0/128hb0/064hb0/ 064ha0/064h80 stacked multi-chip product (mcp) flash memory and psram cmos 3.0 volt-only, simultaneous operation flash memories and static ram/pseudo-static ram
2 s71jl128hc0/128hb0/064hb0/064ha0/064h80 s71jlxxxhxx_00a3 may 25, 2004 preliminary product selector guide device-model # sram/psram density sram/psram type supplier flash access time (ns) ram access time (ns) packages s71jl064h80bxx01 8mb sram - x8/x16 supplier 1 70 70 flb073 s71jl064h80bxx02 8mb sram - x8/x16 supplier 1 85 85 flb073 s71jl064h80bxx10 8mb psram - x16 supplier 2 55 55 flj073 s71jl064h80bxx11 8mb psram - x16 supplier 2 70 70 flj073 s71jl064h80bxx12 8mb psram - x16 supplier 2 85 85 flj073 s71jl064ha0bxx01 16mb sram - x16 supplier 1 70 70 flb073 s71jl064ha0bxx02 16mb sram - x16 supplier 1 85 85 flb073 s71jl064ha0bxx10 16mb psram - x16 supplier 2 55 55 flj073 s71jl064ha0bxx11 16mb psram - x16 supplier 2 70 70 flj073 s71jl064ha0bxx12 16mb psram - x16 supplier 2 85 85 flj073 s71jl064ha0bxx62 16mb psram - x16 supplier 4 70 70 flj073 s71jl128hb0bxx01 32mb psram - x16 supplier 3 70 70 fta073 s71jl128hb0bxx02 32mb psram - x16 supplier 3 85 85 fta073 s71jl128hc0bxx01 64mb psram - x16 supplier 3 70 70 fta088 s71jl128hc0bxx02 64mb psram - x16 supplier 3 85 85 fta088
may 25, 2004 s71jlxxxhxx_00a3 3 advance information table of contents s71jl128hc0/128hb0/064hb0/064ha0/064h80 distinctive characteristics . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 product selector guide . . . . . . . . . . . . . . . . . . . . . .2 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 mcp block diagram of s71jl064h80, model numbers 01/02 ................7 mcp block diagram of s71jl064h80, model numbers 10/11/12 ..............7 mcp block diagram of s71jl064ha0, model numbers 01/02 ................8 mcp block diagram of s71jl064ha0, model numbers 10/11/12/62 .......8 mcp block diagram of s71jl064hb0, model numbers 00/01/02 ..........9 mcp block diagram of s71jl128hb0, model numbers 00/01/02 ......... 10 mcp block diagram of s71jl128hc0, model numbers 00/01/02 ......... 11 connection diagrams . . . . . . . . . . . . . . . . . . . . . 12 connection diagram of s71jl064h80, model numbers 01/02 ............. 12 special package handling instructions .......................................................13 pin description .................................................................................................13 logic symbol .................................................................................................... 14 connection diagram of s71jl064h80, model numbers 10/11/12 ............15 pin description ................................................................................................ 16 logic symbol .................................................................................................... 16 connection diagram of s71jl064ha0, model numbers 01/02 ..............17 pin description ................................................................................................ 18 logic symbol .................................................................................................... 19 connection diagram of s71jl064ha0, model numbers 10/11/12/62 ... 20 pin description ................................................................................................ 21 logic symbol .................................................................................................... 21 connection diagram of s71jl064hb0, model numbers 00/01/02 ...... 22 pin description ................................................................................................23 logic symbol ....................................................................................................23 connection diagram of s71jl128hb0, model numbers 00/01/02 ....... 24 pin description ................................................................................................25 logic symbol ....................................................................................................25 connection diagram of s71jl128hc0, model numbers 00/01/02 ...... 26 special package handling instructions ..................................................... 26 pin description ................................................................................................27 logic symbol ....................................................................................................27 look-ahead connection diagram ................................................................. 28 ordering information . . . . . . . . . . . . . . . . . . . . . . .30 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 34 flb073 ....................................................................................................................34 flj073 ......................................................................................................................35 fta073 ...................................................................................................................36 fta088 ..................................................................................................................37 s29jl064h general description 2 product selector guide . . . . . . . . . . . . . . . . . . . . . .4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 device bus operations . . . . . . . . . . . . . . . . . . . . . . .6 table 1. s29jl064h device bus operations ............................ 6 word/byte configuration .................................................................................. 7 requirements for reading array data ...........................................................7 writing commands/command sequences ...................................................7 accelerated program operation ................................................................. 8 autoselect functions ....................................................................................... 8 simultaneous read/write operations with zero latency ..................... 8 standby mode .........................................................................................................9 automatic sleep mode ....................................................................................... 9 reset#: hardware reset pin ........................................................................... 9 output disable mode ........................................................................................10 table 2. s29jl064h sector architecture ............................... 11 table 3. bank address ........................................................ 14 table 4. secsi tm sector addresses ....................................... 14 autoselect mode ................................................................................................. 14 sector/sector block protection and unprotection .................................. 15 table 5. s29jl064h boot sector/sector block addresses for protection/unprotection ...................................................... 15 write protect (wp#) ........................................................................................ 17 table 6. wp#/acc modes ................................................... 17 temporary sector unprotect ......................................................................... 17 figure 1. temporary sector unprotect operation ................... 18 figure 2. in-system sector protect/unprotect algorithms ....... 19 secsi? (secured silicon) sector flash memory region ........................................................................................20 figure 3. secsi sector protect verify .................................... 21 hardware data protection .............................................................................. 21 low vcc write inhibit ................................................................................. 21 write pulse ?glitch? protection ............................................................... 22 logical inhibit ................................................................................................... 22 power-up write inhibit ............................................................................... 22 common flash memory interface (cfi) . . . . . . . 22 table 1. cfi query identification string ................................ 23 table 7. system interface string ......................................... 23 table 2. device geometry definition .................................... 24 table 3. primary vendor-specific extended query .................. 25 command definitions . . . . . . . . . . . . . . . . . . . . . . 26 reading array data ........................................................................................... 26 reset command ................................................................................................. 26 autoselect command sequence .................................................................... 27 enter secsi? sector/exit secsi sector command sequence .......................................................................................... 27 byte/word program command sequence ................................................. 27 unlock bypass command sequence ........................................................28 figure 4. program operation ............................................... 29 chip erase command sequence ................................................................... 29 sector erase command sequence ................................................................ 30 figure 5. erase operation ................................................... 31 erase suspend/erase resume commands ................................................... 31 table 4. s29jl064h command definitions ............................ 33 write operation status . . . . . . . . . . . . . . . . . . . . . 34 dq7: data# polling ............................................................................................ 34 figure 6. data# polling algorithm ........................................ 35 ry/by#: ready/ busy# ........................................................................................36 dq6: toggle bit i ............................................................................................... 36 figure 7. toggle bit algorithm ............................................. 37 dq2: toggle bit ii .............................................................................................. 37 reading toggle bits dq6/dq2 ..................................................................... 38 dq5: exceeded timing limits ........................................................................ 38 dq3: sector erase timer ................................................................................ 38 table 8. write operation status ........................................... 39 absolute maximum ratings . . . . . . . . . . . . . . . . . 40 figure 8. maximum negative overshoot waveform ................ 40 figure 9. maximum positive overshoot waveform .................. 40
4 s71jlxxxhxx_00a3 may 25, 2004 advance information operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 40 wireless (w) devices .................................................................................. 40 industrial (i) devices ..................................................................................... 40 v cc supply voltages ..................................................................................... 40 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 41 cmos compatible ............................................................................................. 41 zero-power flash ........................................................................................... 42 figure 10. i cc1 current vs. time (showing active and automatic sleep currents)................................................... 42 figure 11. typical i cc1 vs. frequency.................................... 42 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 12. test setup ........................................................ 43 key to switching waveforms . . . . . . . . . . . . . . . .43 figure 13. input waveforms and measurement levels............. 43 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . .44 read-only operations .................................................................................... 44 figure 14. read operation timings ....................................... 44 hardware reset (reset#) ...............................................................................45 figure 15. reset timings ..................................................... 45 word/byte configuration (byte#) ............................................................. 46 figure 16. byte# timings for read operations ...................... 47 figure 17. byte# timings for write operations ...................... 47 erase and program operations ..................................................................... 48 figure 18. program operation timings .................................. 49 figure 19. accelerated program timing diagram .................... 49 figure 20. chip/sector erase operation timings ..................... 50 figure 21. back-to-back read/write cycle timings ................. 51 figure 22. data# polling timings (during embedded algorithms) . 51 figure 23. toggle bit timings (during embedded algorithms) .. 52 figure 24. dq2 vs. dq6 ...................................................... 52 temporary sector unprotect .........................................................................53 figure 25. temporary sector unprotect timing diagram.......... 53 figure 26. sector/sector block protect and unprotect timing diagram................................................... 54 alternate ce# controlled erase and program operations ..................55 figure 27. alternate ce# controlled write (erase/program) operation timings .............................................................. 56 erase and programming performance . . . . . . . . 57 16 mb sram (supplier 1) functional description . . . . . . . . . . . . . . . . . . . . . 59 absolute maximum ratings . . . . . . . . . . . . . . . . . 59 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60 recommended dc operating conditions (note 1) ............................... 60 capacitance (f=1mhz, t a =25 c) ................................................................... 60 dc operating characteristics ....................................................................... 60 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 61 read/write charcteristics (v cc =2.7-3.3v) ................................................. 61 data retention characteristics ...................................................................... 61 timing diagrams ................................................................................................. 62 figure 28. timing waveform of read cycle(1) (address controlled, cd#1=oe#=v il , cs2=we#=v ih , ub# and/or lb#=v il )......... 62 figure 29. timing waveform of read cycle(2) (we#=v ih )....... 62 figure 30. timing waveform of write cycle(1) (we# controlled) .. 63 figure 31. timing waveform of write cycle(2) (cs# controlled) ... 63 figure 32. timing waveform of write cycle(3) (ub#, lb# controlled) ........................................................................ 64 figure 33. data retention waveform .................................... 65 8 mb psram (supplier 2) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 general description . . . . . . . . . . . . . . . . . . . . . . . 67 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 34. functional block diagram .................................... 68 table 9. functional description ............................................ 68 absolute maximum ratings (see note) . . . . . . . 68 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 69 operating characteristics (over specified temperature range) ....... 69 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 69 table 10. timing test conditions ......................................... 69 table 11. timings .............................................................. 70 timing diagrams .................................................................................................. 71 figure 35. timing of read cycle (ce1# = oe# = v il , we# = ce2 = v ih ) .............................................................................. 71 figure 36. timing waveform of read cycle (we# = v ih ) ........ 71 figure 37. timing waveform of write cycle (we# control) ..... 72 figure 38. timing waveform of write cycle (ce1# control)..... 72 16 mb psram (supplier 2) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 general description . . . . . . . . . . . . . . . . . . . . . . . 73 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 39. functional block diagram .................................... 74 table 12. functional description .......................................... 74 absolute maximum ratings (see note) . . . . . . . 75 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 75 operating characteristics (over specified temperature range) ....... 75 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 76 timing test conditions .................................................................................... 76 timings ................................................................................................................... 76 timings ................................................................................................................... 77 figure 40. timing of read cycle (ce1# = oe# = v il , we# = ce2 = v ih ) .............................................................................. 77 figure 41. timing waveform of read cycle (we# = v ih ) ........ 77 figure 42. timing waveform of write cycle (we# control) ..... 78 figure 43. timing waveform of write cycle (ce1# control, ce2 = high) ............................................................................... 78 16 mb psram (supplier 4) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . 80 absolute maxumum ratings (see note) . . . . . . 80 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 80 table 13. dc recommended operating conditions ................. 80 table 14. dc characteristics (t a = -25 c to 85 c, vdd = 2.6 to 3.3v) ............................................................................... 81 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 81 table 15. ac characteristics and operating conditions (t a = -25 c to 85 c, v dd = 2.6 to 3.3v) ................................................ 81 table 16. ac test conditions ............................................... 82 figure 44. ac test loads .................................................... 82 figure 45. state diagram ................................................... 83 table 17. standby mode characteristics ................................ 83 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 46. read cycle 1?addressed controlled ..................... 83 figure 47. read cycle 2?cs1# controlled ............................ 84
may 25, 2004 s71jlxxxhxx_00a3 5 advance information figure 48. write cycle 1?we# controlled ............................. 84 figure 49. write cycle 2?cs1# controlled ............................ 85 figure 50. write cycle3?ub#, lb# controlled ....................... 85 figure 51. deep power-down mode....................................... 86 figure 52. power-up mode ................................................... 86 figure 53. abnormal timing................................................. 86 32 mb psram (supplier 3) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . 88 absolute maxumum ratings . . . . . . . . . . . . . . . . 88 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 88 table 18. dc recommended operating conditions (t a = -40 c to 85 c) ............................................................................... 88 table 19. dc characteristics (t a = -40 c to 85 c, vdd = 2.6 to 3.3v) ............................................................................... 89 table 20. capacitance (t a = 25 c, f = 1 mhz) ....................... 89 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 89 table 21. ac characteristics and operating conditions (t a = -40 c to 85 c, v dd = 2.6 to 3.3v) ................................................ 89 table 22. ac test conditions .............................................. 90 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 54. read cycle ......................................................... 91 figure 55. page read cycle (8 words access) ......................... 92 figure 56. write cycle 1 (we# controlled) ............................. 93 figure 57. write cycle 2 (ce# controlled).............................. 94 figure 58. deep power-down timing..................................... 94 figure 59. power-on timing ................................................. 94 figure 60. read address skew provisions .............................. 95 figure 61. write address skew provisions.............................. 95 64 mb psram (supplier 3) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . 98 absolute maxumum ratings . . . . . . . . . . . . . . . . 98 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 98 table 23. dc recommended operating conditions (t a = -25 c to 85 c) ............................................................................... 98 table 24. dc characteristics (t a = -25 c to 85 c, vdd = 2.6 to 3.3v) ............................................................................... 99 table 25. capacitance (t a = 25 c, f = 1 mhz) ....................... 99 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 99 table 26. ac characteristics and operating conditions (t a = -25 c to 85 c, v dd = 2.6 to 3.3v) ................................................ 99 table 27. ac test conditions ............................................. 100 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 62. read cycle ...................................................... 101 figure 63. page read cycle (8 words access) ...................... 102 figure 64. write cycle 1 (we# controlled) .......................... 103 figure 65. write cycle 2 (ce# controlled) ........................... 104 figure 66. deep power-down timing .................................. 104 figure 67. power-on timing .............................................. 104 figure 68. read address skew provisions ........................... 105 figure 69. write address skew provisions ........................... 105 8 mb sram (supplier 1) functional description . . . . . . . . . . . . . . . . . . . . . 107 table 28. word mode ....................................................... 107 table 29. byte mode ........................................................ 107 absolute maximum ratings . . . . . . . . . . . . . . . 108 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 108 recommended dc operating conditions ............................................... 108 capacitance (f=1mhz, t a =25 c) ................................................................. 108 dc and operating characteristics ............................................................. 109 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 110 read/write charcteristics (v cc =2.7-3.3v) ................................................110 data retention characteristics .....................................................................110 timing diagrams ..................................................................................................111 figure 70. timing waveform of read cycle(1) (address controlled, cd#1=oe#=v il , cs2=we#=v ih , ub# and/or lb#=v il ) ...... 111 figure 71. timing waveform of read cycle(2) (we#=v ih , if byte# is low, ignore ub#/lb# timing) ......................................... 111 figure 72. timing waveform of write cycle(1) (we# controlled, if byte# is low, ignore ub#/lb# timing) ............................... 111 figure 73. timing waveform of write cycle(2) (ce1# controlled, if byte# is low, ignore ub#/lb# timing) ............................... 112 figure 74. timing waveform of write cycle(3) (ub#, lb# controlled, byte# must be high) ....................................... 112 data retention waveforms ............................................................................ 113 figure 75. ce1# controlled............................................... 113 figure 76. cs2 controlled ................................................. 113 revision summary
6 s71jlxxxhxx_00a3 may 25, 2004 advance information
may 25, 2004 s71jlxxxhxx_00a3 7 preliminary block diagrams mcp block diagram of s71jl064h80, model numbers 01/02 mcp block diagram of s71jl064h80, model numbers 10/11/12 v ss v cc s reset# we# ce#f oe# ce1#s v ss v cc f ry/by# lb# ub# ciof wp#/acc ce2s sa cios 8 mbit sram 64 mbit flash memory dq15/a-1 to dq0 dq15/a-1 to dq0 dq15/a ? 1 to dq0 a21 to a0 a21 to a0 a0 to a19 a ? 1 a18 to a0 v ss v cc s reset# we# oe# ce1#s v ss v cc f ry/by# lb# ub# ce2s 8 mbit psram 64 mbit flash memory dq15 to dq0 dq15 to dq0 dq15 to dq0 a21 to a0 a0 to a19 ce#f wp#/acc a18 to a0 a21 to a0 ry/by#
8 s71jlxxxhxx_00a3 may 25, 2004 preliminary mcp block diagram of s71jl064ha0, model numbers 01/02 mcp block diagram of s71jl064ha0, model numbers 10/11/12/62 v ss v cc s reset# we# ce#f oe# ce1#s v ss v cc f ry/by# lb# ub# wp#/acc ce2s 16 mbit sram 64 mbit flash memory dq15 to dq0 dq15 to dq0 dq15 to dq0 a21 to a0 a21 to a0 a0 to a19 a19 to a0 v ss v cc s reset# we# ce#f oe# ce1#s v ss v cc f ry/by# lb# ub# wp#/acc ce2s 16 mbit psram 64 mbit flash memory dq15 to dq0 dq15 to dq0 dq15 to dq0 a21 to a0 a21 to a0 a0 to a19 a19 to a0
may 25, 2004 s71jlxxxhxx_00a3 9 preliminary mcp block diagram of s71jl064hb0, model numbers 00/01/02 v ss v cc s reset# we# ce#f oe# ce1#s v ss v cc f ry/by# lb# ub# wp#/acc ce2s 16 mbit psram 64 mbit flash memory dq15 to dq0 dq15 to dq0 dq15 to dq0 a21 to a0 a21 to a0 a0 to a19 a20 to a0
10 s71jlxxxhxx_00a3 may 25, 2004 preliminary mcp block diagram of s71jl128hb0, model numbers 00/01/02 v ss v cc s reset# we# oe# ce1#s lb# ub# ce#f1 wp#/acc ce2s 32 mbit psram 64 mbit flash memory #2 dq15 to dq0 dq15 to dq0 v ss v cc f 64 mbit flash memory #1 a20 to a0 a21 to a0 a21 to a0 ce#f2 dq15 to dq0 v ss v cc f ry/by# a21 to a0 dq15 to dq0
may 25, 2004 s71jlxxxhxx_00a3 11 preliminary mcp block diagram of s71jl128hc0, model numbers 00/01/02 v ss v cc s reset#2 we# oe# ce1#ps lb# ub# ce#f1 wp#/acc ce2ps 64 mbit psram 64 mbit flash memory #2 dq15 to dq0 dq15 to dq0 ry/by#1 v ss v cc f 64 mbit flash memory #1 a21 to a0 a21 to a0 a21 to a0 dq15 to dq0 v ss v cc f ry/by#2 reset#1 ce#f2 a21 to a0 dq15 to dq0
12 s71jlxxxhxx_00a3 may 25, 2004 preliminary connection diagrams connection diagram of s71jl064h80, model numbers 01/02 a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s cios a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 sa dq15/a-1 dq7 dq14 a15 a21 nc a16 ciof v ss nc nc nc nc nc nc sram only shared flash only 73-ball fbga to p v i e w
may 25, 2004 s71jlxxxhxx_00a3 13 preliminary special package handling instructions special handling is required for flash memory products in molded packages (fbga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. pin description a18?a0 = 19 address inputs (common) a21?a19, a-1 = 4 address inputs (flash) sa = highest order address pin (sram) byte mode dq15?dq0 = 16 data inputs/outputs (common) ce#f = chip enable (flash) ce#s = chip enable (sram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output ub# = upper byte control (sram) lb# = lower byte control (sram) ciof = i/o configuration (flash) ciof = v ih = word mode (x16), ciof = v il = byte mode (x8) cios = i/o configuration (sram) cios = v ih = word mode (x16), cios = v il = byte mode (x8) reset# = hardware reset pin, active low wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v cc s = sram power supply v ss = device ground (common) nc = pin not connected internally
14 s71jlxxxhxx_00a3 may 25, 2004 preliminary logic symbol 19 16 or 8 dq15?dq0 a18?a0 ce#f oe# we# reset# ub# ry/by# wp#/acc sa a21?a19, a-1 lb# ciof cios ce1#s ce2s
may 25, 2004 s71jlxxxhxx_00a3 15 preliminary connection diagram of s71jl064h80, model numbers 10/11/12 a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s nc a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 nc dq15 dq7 dq14 a15 a21 nc a16 nc v ss nc nc nc nc nc nc sram only shared flash only 73-ball fbga to p v i e w
16 s71jlxxxhxx_00a3 may 25, 2004 preliminary special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga, pdip, ssop, plcc). the pack age and/or data integrity may be com - promised if the package body is exposed to temperatures above 150 c for prolonged periods of time. pin description a18?a0 = 19 address inputs (common) a21?a19 = 2 address inputs (flash) dq15?dq0 = 16 data inputs/outputs (common) ce#f = chip enable (flash) ce1#s = chip enable 1 (psram) ce2s = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output ub# = upper byte control (psram) lb# = lower byte control (psram) reset# = hardware reset pin, active low wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v cc s = psram power supply v ss = device ground (common) nc = pin not connected internally logic symbol 19 16 dq15?dq0 a18?a0 ce#f oe# we# reset# ub# ry/by# wp#/acc sa a21, a19 lb# ce1#s ce2s
may 25, 2004 s71jlxxxhxx_00a3 17 preliminary connection diagram of s71jl064ha0, model numbers 01/02 a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s nc a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 nc dq15 dq7 dq14 a15 a21 nc a16 nc v ss nc nc nc nc nc nc sram only shared flash only 73-ball fbga to p v i e w
18 s71jlxxxhxx_00a3 may 25, 2004 preliminary special package handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages ma y be damaged if exposed to ultrasonic cleaning methods. the package and/or da ta integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. pin description a19?a0 = 20 address inputs (common) a21?a20 = 2 address inputs (flash) dq15?dq0 = 16 data inputs/outputs (common) ce#f = chip enable (flash) ce#s = chip enable (sram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output ub# = upper byte control (sram) lb# = lower byte control (sram) reset# = hardware reset pin, active low wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v cc s = sram power supply v ss = device ground (common) nc = pin not connected internally
may 25, 2004 s71jlxxxhxx_00a3 19 preliminary logic symbol 20 16 dq15?dq0 a19?a0 ce#f oe# we# reset# ub# ry/by# wp#/acc a21?a20 lb# ce1#s ce2s
20 s71jlxxxhxx_00a3 may 25, 2004 preliminary connection diagram of s71jl064ha0, model numbers 10/11/12/62 a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s nc a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 nc dq15 dq7 dq14 a15 a21 nc a16 nc v ss nc nc nc nc nc nc sram only shared flash only 73-ball fbga to p v i e w
may 25, 2004 s71jlxxxhxx_00a3 21 preliminary special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga, pdip, ssop, plcc). the pack age and/or data integrity may be com - promised if the package body is exposed to temperatures above 150 c for prolonged periods of time. pin description a19?a0 = 20 address inputs (common) a21?a20 = 2 address inputs (flash) dq15?dq0 = 16 data inputs/outputs (common) ce#f = chip enable (flash) ce1#s = chip enable 1 (psram) ce2s = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output ub# = upper byte control (psram) lb# = lower byte control (psram) reset# = hardware reset pin, active low wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v cc s = psram power supply v ss = device ground (common) nc = pin not connected internally logic symbol 20 16 dq15?dq0 a19?a0 ce#f oe# we# reset# ub# ry/by# wp#/acc sa lb# ce1#s ce2s
22 s71jlxxxhxx_00a3 may 25, 2004 preliminary connection diagram of s71jl064hb0, model numbers 00/01/02 a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s nc a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 nc dq15 dq7 dq14 a15 a21 nc a16 nc v ss nc nc nc nc nc nc sram only shared flash only 73-ball fbga to p v i e w
may 25, 2004 s71jlxxxhxx_00a3 23 preliminary special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga, pdip, ssop, plcc). the pack age and/or data integrity may be com - promised if the package body is exposed to temperatures above 150 c for prolonged periods of time. pin description a20?a0 = 20 address inputs (common) a21 = 1 address input (flash) dq15?dq0 = 16 data inputs/outputs (common) ce#f = chip enable (flash) ce1#s = chip enable 1 (psram) ce2s = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output ub# = upper byte control (psram) lb# = lower byte control (psram) reset# = hardware reset pin, active low wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v cc s = psram power supply v ss = device ground (common) nc = pin not connected internally logic symbol 21 16 dq15?dq0 a20?a0 ce#f oe# we# reset# ub# ry/by# wp#/acc sa a21 lb# ce1#s ce2s
24 s71jlxxxhxx_00a3 may 25, 2004 preliminary connection diagram of s71jl128hb0, model numbers 00/01/02 flash 2 only a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 h 2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f1 ce1#s a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2s a20 dq4 v cc s nc a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 nc dq15 dq7 dq14 a15 a21 ce#f2 a16 nc v ss nc nc nc nc nc nc flash 1 only flash 1 and 2 shared flash 1, 2, and pseudo sram shared pseudo sram only 73-ball fbga to p v i e w
may 25, 2004 s71jlxxxhxx_00a3 25 preliminary special package handling instructions special handling is required for flash memory products in molded packages (bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. pin description a20?a0 = 21 address inputs (common) a21 = 1 address input (flash) dq15?dq0 = 16 data inputs/outputs (common) ce#f1 = chip enable 1 (flash 1) ce#f2 = chip enable 2 (flash 2) ce1#ps = chip enable 1 (psram) ce2ps = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output ub# = upper byte control (psram) lb# = lower byte control (psram) reset# = hardware reset pin, active low wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v cc ps = psram power supply v ss = device ground (common) nc = pin not connected internally logic symbol ce1#ps 21 16 dq15?dq0 a20?a0 ce#f1 oe# we# reset# ub# ry/by# wp#/acc a21 lb# ce#f2 ce2ps
26 s71jlxxxhxx_00a3 may 25, 2004 preliminary connection diagram of s71jl128hc0, model numbers 00/01/02 special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga, plcc, pdip, ssop). the pack age and/or data in tegrity may be com - promised if the package body is exposed to temperatures above 150 c for prolonged periods of time. h4 h5 h6 h7 h8 h9 g7 g8 g9 f7 f8 f9 e7 e8 e9 d7 d8 d9 c5 j2 j 2 j3 h2 h 2 c6 c7 ce#f1 h3 oe# ce1#fs dq0 c2 c3 b2 b3 nc vss nc a7 a8 we# wp#/acc lb# b4 b 4 b5 b 5 b6 b7 c8 c9 nc a11 b8 b9 nc nc nc nc ce#f2 ry/by#2 a15 a12 a19 a21 a13 a9 nc a14 a10 a16 nc dq6 g6 f6 e6 ce2s a20 nc nc g4 g5 f4 f5 e4 e5 d5 reset#1 ub# ry/by#1 a18 nc a17 nc dq1 nc dq15 dq13 dq4 dq3 dq9 j4 j5 j 5 j7 j8 j9 dq7 v cc s v cc f dq10 g2 g3 f2 f3 e2 e3 d2 d3 a6 a3 a5 a2 a4 a1 v ss a0 k4 k5 k6 k7 k8 k9 k2 k3 l2 nc dq8 nc reset#2 v ss dq12 nc dq14 dq5 nc dq11 dq2 l4 l5 l6 l7 l8 l9 nc nc nc v cc f v ss a1 nc a10 nc nc m10 nc m1 nc flash 1 and 2 shared shared flash 1 only flash 2 only sram only j4 j4 j 4 h2 c4 c 4 d4 d 4 d6 d 6 m2 nc m9 nc a9 nc a2 nc l3 l 3 88-ball fine-pitch ball grid array (top view, balls facing down)
may 25, 2004 s71jlxxxhxx_00a3 27 preliminary pin description a21?a0 = 22 address inputs (common) dq15?dq0 = 16 data inputs/outputs (common) ce#f1 = chip enable 1 (flash 1) ce#f2 = chip enable 2 (flash 2) ce1#ps = chip enable 1 (psram) ce2ps = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by#1 = ready/busy output (flash 1) ry/by#2 = ready/busy output (flash 2) ub# = upper byte control (psram) lb# = lower byte control (psram) reset#1 = hardware reset pin, active low (flash 1) reset#2 = hardware reset pin, active low (flash 2) wp#/acc = hardware write protect/acceleration pin (flash) v cc f = flash 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v cc ps = psram power supply v ss = device ground (common) nc = pin not connected internally logic symbol 22 16 dq15?dq0 a21?a0 ce#f1 oe# we# reset#1 reset#2 ry/by#1 wp#/acc ub# ce#f2 ce2ps ce1#ps lb# ry/by#2
28 s71jlxxxhxx_00a3 may 25, 2004 preliminary look-ahead connection diagram note: to provide customers with a migration path to higher densities and an option to stack more die in a package, fasl has prepared a standard pinout that supports ? nor flash and sram densities up to 4 gigabits ? nor flash and psram densities up to 4 gigabits j4 j5 j6 j7 j8 j2 h7 h8 h9 g7 g8 g9 f7 f8 f9 e7 e8 e9 d5 k2 k3 d6 d7 ce#f1 j3 oe# ce1#s1 dq0 d2 d3 c2 c3 avd# vssds wp# a7 a8 we# wp#/acc lb#s c4 c5 c6 c7 d8 d9 ce1#ds a11 c8 c9 ry/by#ds clkds reset#ds vccds ce#f2 clk a15 a12 a19 a21 a13 a9 a22 a14 a10 a16 a24 dq6 h6 g6 f6 ce2s1 a20 a23 ce2s2 h4 h5 g4 g5 f4 f5 e5 reset#f ub#s ry/by# a18 ce1#s2 a17 vccs2 dq1 cres dq15 dq13 dq4 dq3 dq9 k4 k5 k 5 k7 k8 k9 dq7 vccs1 vccf dq10 h2 h3 g2 g3 f2 f3 e2 e3 a6 a3 a5 a2 a4 a1 vss a0 l4 l5 l6 l7 l8 l9 l2 l3 m2 m3 vccds dq8 a27 a26 vss dq12 lock or wp#/accds dq14 dq5 a25 dq11 dq2 m4 m5 m6 m7 m8 m9 vccqds vccqs1 ce2#ds vccf or vccqf vssnds test n10 nc n1 nc legend: k5 k6 d4 b2 nc a2 nc b1 a1 nc nc b9 nc a9 nc b10 nc a10 nc p9 nc n9 nc p10 nc n2 nc p1 nc p2 nc j2 e4 e6 ds = data storage only f = flash shared only f1 = 1st flash only f2 = 2nd flash only nc = outrigger balls s = ram shared s1 = 1st ram only s2 = 2nd ram only 96 - b a ll fi ne- pit c h b a ll g r id a rray (top view, balls facing down)
may 25, 2004 s71jlxxxhxx_00a3 29 preliminary ? nor flash and psram and data storage densities up to 4 gigabits the signal locations of the resultant mcp device are shown above. note that for different densities, the actual package outline may vary. any pinout in any mcp, however, will be a subset of the pinout above. in some cases, there may be outrigger balls in locations outside the grid shown above. in such cases, the user is rec - ommended to treat them as reserved and not connect them to any other signal. for any further inquiries about the above look-ahead pinout, please refer to the application note on this subject or con - tact your sales office.
30 s71jlxxxhxx_00a3 may 25, 2004 preliminary ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s71 jl064ha0baw000 packing type 0=tray 2=7? tape & reel 3 = 13? tape & reel additional ordering options see product selector guide temperature (and reliability) grade e = engineering samples w = wireless (-25 c to +85 c) i=industrial (-40 c to +85 c) package material set (bga package type) a = standard (pb-free compliant) package f = lead (pb)-free package package type b=bga package chip contents?2 0 = no second content chip contents?1 8=8 mb a = 16 mb b = 32 mb c = 64 mb spansion flash memory process technology (highest-density flash described in characters 4-8) h = 130 nm floating gate technology base nor flash density 064 = one s29jl064h 128 = two s29jl064h base nor flash core voltage l=3-volt v cc base nor flash interface and simultaneous read/ write j = simultaneous read/write product family 71 = flash base + xram. prefix s=spansion valid combinations flash access time (ns) (p)sram access time (ns) temperature range supplier order number package marking s71jl064h80bai01 71jl064h80bai01 70 70 -40c to +85c supplier 1 s71jl064h80bai02 71jl064h80bai02 85 85 -40c to +85c supplier 1 s71jl064h80bai10 71jl064h80bai10 55 55 -40c to +85c supplier 2 s71jl064h80bai11 71jl064h80bai11 70 70 -40c to +85c supplier 2
may 25, 2004 s71jlxxxhxx_00a3 31 preliminary s71jl064h80bai12 71jl064h80bai12 85 85 -40c to +85c supplier 2 s71jl064h80baw01 71jl064h80baw01 70 70 -25c to +85c supplier 1 s71jl064h80baw02 71jl064h80baw02 85 85 -25c to +85c supplier 1 s71jl064h80baw10 71jl064h80baw10 55 55 -25c to +85c supplier 2 s71jl064h80baw11 71jl064h80baw11 70 70 -25c to +85c supplier 2 s71jl064h80baw12 71jl064h80baw12 85 85 -25c to +85c supplier 2 s71jl064h80bfi01 71jl064h80bfi01 70 70 -40c to +85c supplier 1 s71jl064h80bfi02 71jl064h80bfi02 85 85 -40c to +85c supplier 1 s71jl064h80bfi10 71jl064h80bfi10 55 55 -40c to +85c supplier 2 s71jl064h80bfi11 71jl064h80bfi11 70 70 -40c to +85c supplier 2 s71jl064h80bfi12 71jl064h80bfi12 85 85 -40c to +85c supplier 2 s71jl064h80bfw01 71jl064h80bfw01 70 70 -25c to +85c supplier 1 s71jl064h80bfw02 71jl064h80bfw02 85 85 -25c to +85c supplier 1 s71jl064h80bfw10 71jl064h80bfw10 55 55 -25c to +85c supplier 2 s71jl064h80bfw11 71jl064h80bfw11 70 70 -25c to +85c supplier 2 s71jl064h80bfw12 71jl064h80bfw12 85 85 -25c to +85c supplier 2 s71jl064ha0bai01 71jl064ha0bai01 70 70 -40c to +85c supplier 1 s71jl064ha0bai02 71jl064ha0bai02 85 85 -40c to +85c supplier 1 s71jl064ha0bai10 71jl064ha0bai10 55 55 -40c to +85c supplier 2 s71jl064ha0bai11 71jl064ha0bai11 70 70 -40c to +85c supplier 2 s71jl064ha0bai12 71jl064ha0bai12 85 85 -40c to +85c supplier 2 s71jl064ha0bai62 71jl064ha0bai62 70 70 -40c to +85c supplier 4 s71jl064ha0baw01 71jl064ha0baw01 70 70 -25c to +85c supplier 1 s71jl064ha0baw02 71jl064ha0baw02 85 85 -25c to +85c supplier 1 s71jl064ha0baw10 71jl064ha0baw10 55 55 -25c to +85c supplier 2 s71jl064ha0baw11 71jl064ha0baw11 70 70 -25c to +85c supplier 2 s71jl064ha0baw12 71jl064ha0baw12 85 85 -25c to +85c supplier 2 s71jl064ha0baw62 71jl064ha0baw62 70 70 -25c to +85c supplier 4 s71jl064ha0bfi01 71jl064ha0bfi01 70 70 -40c to +85c supplier 1 s71jl064ha0bfi02 71jl064ha0bfi02 85 85 -40c to +85c supplier 1 s71jl064ha0bfi10 71jl064ha0bfi10 55 55 -40c to +85c supplier 2 s71jl064ha0bfi11 71jl064ha0bfi11 70 70 -40c to +85c supplier 2 s71jl064ha0bfi12 71jl064ha0bfi12 85 85 -40c to +85c supplier 2 s71jl064ha0bfi62 71jl064ha0bfi62 70 70 -40c to +85c supplier 4 valid combinations flash access time (ns) (p)sram access time (ns) temperature range supplier order number package marking
32 s71jlxxxhxx_00a3 may 25, 2004 preliminary s71jl064ha0bfw01 71jl064ha0bfw01 70 70 -25c to +85c supplier 1 s71jl064ha0bfw02 71jl064ha0bfw02 85 85 -25c to +85c supplier 1 s71jl064ha0bfw10 71jl064ha0bfw10 55 55 -25c to +85c supplier 2 s71jl064ha0bfw11 71jl064ha0bfw11 70 70 -25c to +85c supplier 2 s71jl064ha0bfw12 71jl064ha0bfw12 85 85 -25c to +85c supplier 2 s71jl064ha0bfw62 71jl064ha0bfw62 70 70 -25c to +85c supplier 4 s71jl064hb0bai00 71jl064hb0bai00 55 55 -40c to +85c supplier 3 s71jl064hb0bai01 71jl064hb0bai01 70 70 -40c to +85c supplier 3 s71jl064hb0bai02 71jl064hb0bai02 85 85 -40c to +85c supplier 3 s71jl064hb0baw00 71jl064hb0baw00 55 55 -25c to +85c supplier 3 s71jl064hb0baw01 71jl064hb0baw01 70 70 -25c to +85c supplier 3 s71jl064hb0baw02 71jl064hb0baw02 85 85 -25c to +85c supplier 3 s71jl064hb0bfi00 71jl064hb0bfi00 55 55 -40c to +85c supplier 3 s71jl064hb0bfi01 71jl064hb0bfi01 70 70 -40c to +85c supplier 3 s71jl064hb0bfi02 71jl064hb0bfi02 85 85 -40c to +85c supplier 3 s71jl064hb0bfw00 71jl064hb0bfw00 55 55 -25c to +85c supplier 3 s71jl064hb0bfw01 71jl064hb0bfw01 70 70 -25c to +85c supplier 3 s71jl064hb0bfw02 71jl064hb0bfw02 85 85 -25c to +85c supplier 3 s71jl128hb0bai00 71jl128hb0bai00 55 55 -40c to +85c supplier 3 s71jl128hb0bai01 71jl128hb0bai01 70 70 -40c to +85c supplier 3 s71jl128hb0bai02 71jl128hb0bai02 85 85 -40c to +85c supplier 3 s71jl128hb0baw00 71jl128hb0baw00 55 55 -25c to +85c supplier 3 s71jl128hb0baw01 71jl128hb0baw01 70 70 -25c to +85c supplier 3 s71jl128hb0baw02 71jl128hb0baw02 85 85 -25c to +85c supplier 3 s71jl128hb0bfi00 71jl128hb0bfi00 55 55 -40c to +85c supplier 3 s71jl128hb0bfi01 71jl128hb0bfi01 70 70 -40c to +85c supplier 3 s71jl128hb0bfi02 71jl128hb0bfi02 85 85 -40c to +85c supplier 3 s71jl128hb0bfw00 71jl128hb0bfw00 55 55 -25c to +85c supplier 3 s71jl128hb0bfw01 71jl128hb0bfw01 70 70 -25c to +85c supplier 3 s71jl128hb0bfw02 71jl128hb0bfw02 85 85 -25c to +85c supplier 3 s71jl128hc0bai00 71jl128hc0bai00 55 55 -40c to +85c supplier 3 s71jl128hc0bai01 71jl128hc0bai01 70 70 -40c to +85c supplier 3 valid combinations flash access time (ns) (p)sram access time (ns) temperature range supplier order number package marking
may 25, 2004 s71jlxxxhxx_00a3 33 preliminary s71jl128hc0bai02 71jl128hc0bai02 85 85 -40c to +85c supplier 3 s71jl128hc0baw00 71jl128hc0baw00 55 55 -25c to +85c supplier 3 s71jl128hc0baw01 71jl128hc0baw01 70 70 -25c to +85c supplier 3 s71jl128hc0baw02 71jl128hc0baw02 85 85 -25c to +85c supplier 3 s71jl128hc0bfi00 71jl128hc0bfi00 55 55 -40c to +85c supplier 3 s71jl128hc0bfi01 71jl128hc0bfi01 70 70 -40c to +85c supplier 3 s71jl128hc0bfi02 71jl128hc0bfi02 85 85 -40c to +85c supplier 3 s71jl128hc0bfw00 71jl128hc0bfw00 55 55 -25c to +85c supplier 3 s71jl128hc0bfw01 71jl128hc0bfw01 70 70 -25c to +85c supplier 3 s71jl128hc0bfw02 71jl128hc0bfw02 85 85 -25c to +85c supplier 3 valid combinations flash access time (ns) (p)sram access time (ns) temperature range supplier order number package marking
34 s71jlxxxhxx_00a3 may 25, 2004 preliminary physical dimensions flb073 3188\38.14b n/a 11.60 mm x 8.00 mm package flb 073 nom. --- --- --- 1.40 --- 1.13 max. 8.00 bsc. 11.60 bsc. 12 --- min. 0.95 0.20 8.80 bsc. 7.20 bsc. 10 73 0.30 0.35 0.40 bsc a2,a3,a4,a5,a6,a7,a8,a9 b2,b3,b4,b7,b8,b9 c2,c9,c10,d1,d10,e1,e10 f5,f6,g5,g6,h1,h10 j1,j10,k1,k2, k9,k10,l2,l3,l4,l7,l8,l9 m2,m3,m4,m5,m6,m7,m8,m9 0.25 0.80 bsc me d jedec package symbol a a2 a1 md d1 e e1 n note 0.80 bsc depopulated solder ball matrix size e direction matrix footprint ball pitch ball pitch solder ball placement body size ball height body size body thickness profile ball diameter matrix size d direction ball count matrix footprint ee ed sd/se notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indention or other means. b o bottom view l m ed corner e1 7 se d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd pin a1 7 10 index mark c 0.15 (2x) (2x) c 0.15 b a d e pin a1 corner top view 73x 6 b 0.20 c c c a2 a1 a 0.08 side view 0.15 m c mc ab 0.08
may 25, 2004 s71jlxxxhxx_00a3 35 preliminary flj073 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. not used. 10. a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 3232 \ 16-038.14b package flj 073 jedec n/a 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.40 profile a1 0.25 --- --- ball height a2 0.95 --- 1.13 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 73 ball count b 0.30 0.35 0.40 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9,b2,b3,b4,b7,b8,b9 c2,c9,c10,d1,d10,e1,e10,f5,f6,g5,g6,h1,h10 depopulated solder balls j1,j10,k1,k2,k9,k10,l2,l3,l4,l7,l8,l9 m2,m3,m4,m5,m6,m7,m8,m9 10 index mark 73x c 0.15 (2x) (2x) c 0.15 b a 6 b 0.20 c c cb a m c m 0.15 0.08 d e pin a1 c top view side view corner a2 a1 a 0.08 l m ed corner e1 7 se d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd bottom view pin a1 7
36 s71jlxxxhxx_00a3 may 25, 2004 preliminary fta073 3159\38.14b n/a 11.60 mm x 8.00 mm package fta 073 nom. --- --- --- 1.40 --- 1.11 max. 8.00 bsc. 11.60 bsc. 12 --- min. 1.00 0.25 8.80 bsc. 7.20 bsc. 10 73 0.35 0.40 0.40 bsc a2,a3,a4,a5,a6,a7,a8,a9 b2,b3,b4,b7,b8,b9,c2,c9,c10 d1,d10,e1,e10,f5,f6,g5,g6 h1,h10,j1,j10,k1,k2,k9,k10 l2,l3,l4,l7,l8,l9 m2,m3,m4,m5,m6,m7,m8,m9 0.30 0.80 bsc me d jedec package symbol a a2 a1 md d1 e e1 n note depopulated solder ball matrix size e direction matrix footprint ball pitch 0.80 bsc ball pitch solder ball placement body size ball height body size body thickness profile ball diameter matrix size d direction ball count matrix footprint ee ed sd/se notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indention or other means. b o 10 index mark 73x c 0.15 (2x) (2x) c 0.15 b a 6 b 0.20 c c 0.15 c cab m 0.08 m d e pin a1 c top view side view corner a2 a1 a 0.08 bottom view l m ed corner e1 7 se d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd pin a1 7
may 25, 2004 s71jlxxxhxx_00a3 37 preliminary fta088 3237 \ 16-038.14b package fta 088 jedec n/a 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.40 profile a1 0.25 --- --- ball height a2 1.00 --- 1.11 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 88 ball count b 0.30 0.35 0.40 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a3,a4,a5,a6,a7,a8,b1,b10,c1,c10,d1,d10 depopulated solder balls e1,e10,f1,f10,g1,g10,h1,h10 j1,j10,k1,k10,l1,l10,m3,m4,m5,m6,m7,m8 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. 10 index mark l m 88x ed corner c 0.15 (2x) (2x) c 0.15 e1 7 se b a d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd bottom view 6 b 0.20 c c 0.15 0.08 mc mc ab pin a1 7 d e pin a1 c top view side view corner a2 a1 a 0.08
38 s71jlxxxhxx_00a3 may 25, 2004 preliminary
this document contains information on a product under development at fasl llc. the information is intended to help you evaluate this product. fasl llc reserves the right to change or discontinue work on this proposed product without notice. publication number s29jl064h revision a amendment 1 issue date may 7, 2004 preliminary s29jl064h for multi-chip products (mcp) 64 megabit (8 m x 8-bit/4 m x 16-bit) cmos 3.0 volt-only, simultaneous read/write flash memory distinctive characteristics architectural advantages ? simultaneous read/write operations ? data can be continuously read from one bank while executing erase/program functions in another bank. ? zero latency between read and write operations ? flexible bank architecture ? read may occur in any of the three banks not being written or erased. ? four banks may be grouped by customer to achieve desired bank divisions. ? boot sectors ? top and bottom boot sectors in the same device ? any combination of sectors can be erased ? manufactured on 130 nm process technology ? secsi? (secured silicon) sector: extra 256 byte sector ? factory locked and identifiable: 16 bytes available for secure, random factory electronic serial number; verifiable as factory locked through autoselect function. ? customer lockable: one-time programmable only. once locked, data cannot be changed ? zero power operation ? sophisticated power management circuits reduce power consumed during inactive periods to nearly zero. ? compatible with jedec standards ? pinout and software compatible with single-power- supply flash standard performance characteristics ? high performance ? access time as fast as 55 ns ? program time: 4 s/word typical using accelerated programming function ? ultra low power consumption (typical values) ? 2 ma active read current at 1 mhz ? 10 ma active read current at 5 mhz ? 200 na in standby or automatic sleep mode ? cycling endurance: 1 million cycles per sector typical ? data retention: 20 years typical software features ? supports common flash memory interface (cfi) ? erase suspend/erase resume ? suspends erase operations to read data from, or program data to, a sector that is not being erased, then resumes the erase operation. ? data# polling and toggle bits ? provides a software method of detecting the status of program or erase cycles ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features ? ready/busy# output (ry/by#) ? hardware method for detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method of resetting the internal state machine to the read mode ? wp#/acc input pin ? write protect (wp#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status ? acceleration (acc) function accelerates program timing ? sector protection ? hardware method to prevent any program or erase operation within a sector ? temporary sector unprotect allows changing data in protected sectors in-system
2s29jl064h s29jl064ha1 may 7, 2004 preliminary general description the s29jl064h is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. word mode data appears on dq15?dq0; byte mode data appears on dq7?dq0. the device is designed to be programmed in-system with the standard 3.0 volt v cc supply, and can also be programmed in standard eprom programmers. standard control pins?chip enable (ce#), write enable (we#), and output en - able (oe#)?control normal read and write operations, and avoid bus contention issues. the device requires only a single 3.0 volt power supply for both read and write functions. internally generated and regu lated voltages are provided for the pro - gram and erase operations. simultaneous read/write operations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 mb banks with small and large sectors, and two 24 mb banks of large sectors. sector addresses are fixed, system software can be used to form user-defined bank groups. during an erase/program operation, any of the three non-busy banks may be read from. note that only two banks can operate simultaneously. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately an d simultaneously read from the other bank, with zero latency. this releases the system from waiting for the completion of program or erase operations. the s29jl064h can be organized as both a top and bottom boot sector configuration. s29jl064h features the secsi? (secured silicon) sector is an extra 256 byte sector capable of being permanently locked by fasl or customers. [the secsi customer indicator bit (dq6) is permanently set to 1 if the part has been customer locked and per - manently set to 0 if the part has been factory locked.] this way, customer lockable parts can never be used to replace a factory locked part. factory locked parts provide several options. the secsi sector may store a se - cure, random 16 byte esn (electronic serial number), customer code (programmed through spansion programmin g services), or both. customer lock - able parts may utilize the secsi sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. dms (data management software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by al - bank megabits sector sizes bank 1 8 mb eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword bank 2 24 mb forty-eight 64 kbyte/32 kword bank 3 24 mb forty-eight 64 kbyte/32 kword bank 4 8 mb eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword
may 7, 2004 s29jl064ha1 s29jl064h 3 preliminary lowing removal of eeprom devices. dms will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file struc - tures, as opposed to single-byte modifications. to write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. this is an advantage compared to systems where user- written software must keep track of the old data location, status, logical to phys - ical translation of the data onto the flash memory device (or memory devices), and more. using dms, user-written software does not need to interface with the flash memory directly. instead, the user's software accesses the flash memory by calling one of only six functions. the device offers complete compatibility with the jedec 42.4 sin - gle-power-supply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device is similar to reading from other flash or eprom devices. the host system can detect whether a program or erase operation is complete by using the device status bits: ry/by# pin, dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle has been completed, the device au - tomatically returns to the read mode. the sector erase architecture allows memory sectors to be erased and repro - grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automat - ically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combina - tion of the sectors of memory. this can be achieved in-system or via programming equipment. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consump - tion is greatly reduced in both modes.
4s29jl064h s29jl064ha1 may 7, 2004 preliminary product selector guide block diagram part number s29jl064h speed option standard voltage range: v cc = 2.7?3.6 v 55 70 85 max access time (ns), t acc 55 70 85 ce# access (ns), t ce 55 70 85 oe# access (ns), t oe 25 30 40 bank 1 address bank 2 address l d r / by# bank 1 x-decoder oe# byte# status control dq15 dq0 dq15 dq0 u x u x bank 2 x-decoder y-gate bank 3 x-decoder bank 4 x-decoder y-gate bank 3 address bank 4 address
may 7, 2004 s29jl064ha1 s29jl064h 5 preliminary pin description a21?a0 = 22 addresses dq14?dq0 = 15 data inputs/outputs (x16-only devices) dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable oe# = output enable we# = write enable wp#/acc = hardware write protect/ acceleration pin reset# = hardware reset pin, active low byte# = selects 8-bit or 16-bit mode ry/by# = ready/busy output v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# byte# ry/by# wp#/acc
6s29jl064h s29jl064ha1 may 7, 2004 preliminary device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state mach ine outputs dictate the function of the device. ta b l e 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the fo llowing subsections describe each of these operations in further detail. table 1. s29jl064h device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are a21:a0 in word mode (byte# = v ih ), a21:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector/sector block protection and unprotection? section. 3. if wp#/acc = v il , sectors 0, 1, 140, and 141 remain protected. if wp#/acc = v ih , protection on sectors 0, 1, 140, and 141 depends on whether they were last protected or unprotected using the method described in ?sector/sector block protection and unprotection? . if wp#/acc = v hh , all sectors will be unprotected. operation ce# oe# we# reset# wp#/acc addresses (note 2) dq15?dq8 dq7? dq0 byte# = v ih byte# = v il read l l h h l/h a in d out dq14?dq8 = high- z, dq15 = a-1 d out write l h l h (note 3) a in d in d in standby v cc 0.3 v x x v cc 0.3 v l/h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z reset x x x l l/h x high-z high-z high-z sector protect (note 2) l h l v id l/h sa, a6 = l, a1 = h, a0 = l x x d in sector unprotect (note 2) l h l v id (note 3) sa, a6 = h, a1 = h, a0 = l x x d in temporary sector unprotect x x x v id (note 3) a in d in high-z d in
may 7, 2004 s29jl064ha1 s29jl064h 7 preliminary word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic ?1?, the device is in word con - figuration, dq15?dq0 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq7?dq0 are active and controlled by ce# and oe#. the data i/ o pins dq14?dq8 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. refer to the ac read-only operations table for timing specifications and to 14 for the timing diagram. i cc1 in the dc characteristics table represents the active cur - rent specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whether the device accepts program data in bytes or words. refer to ?word/byte configuration? for more information. the device features an unlock bypass mode to facilitate faster programming. once a bank enters the unlock bypass mode, only two write cycles are required to program a word or byte, instead of four. the ?byte/word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e 3 indicates the address space that each sector occupies. similarly, a ?sector address? is the address bits required to uniquely select a sector. the ?command definitions? section has details on erasing a sector or the entire chip, or suspend - ing/resuming the erase operation. the device address space is divided into four banks. a ?bank address? is the ad - dress bits required to uniquely select a bank. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ac characteristics section contains timing specification ta - bles and timing diagrams for write operations.
8s29jl064h s29jl064ha1 may 7, 2004 preliminary accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc pin. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device automatically enters the afore - mentioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a tw o-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin re - turns the device to normal operation. note that v hh must not be asserted on wp#/acc for operations other than accelerated programming, or device damage may result. in addition, the wp#/acc pin must not be left floating or uncon - nected; inconsistent behavior of the device may result . see ?write protect (wp#)? on page 17. for related information. autoselect functions if the system writes the autoselect co mmand sequence, the device enters the au - toselect mode. the system can then read autoselect codes from the internal register (which is separate from th e memory array) on dq15?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autose - lect command sequence sections for more information. simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while program - ming or erasing in the other bank of memory. an erase operation may also be suspended to read from or program to another location within the same bank (ex - cept the sector being erased). figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. icc6 and icc7 in the dc characteristics table represent the current specifications for read-while-program and read-while-erase, respectively.
may 7, 2004 s29jl064ha1 s29jl064h 9 preliminary standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high im pedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during eras ure or programming, the device draws ac - tive current until the operation is completed. icc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the de - vice automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# con - trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. icc5 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the op - eration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of th e reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current ( icc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm - ware from the flash memory. if reset# is asserted during a program or erase operation, the ry/by# pin re - mains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/ by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the ac characteristics tables for reset# parameters and to 15 for the timing diagram.
10 s29jl064h s29jl064ha1 may 7, 2004 preliminary output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
may 7, 2004 s29jl064ha1 s29jl064h 11 preliminary ta b l e 2 . s29jl064h sector architecture bank sector sector address a21?a12 sector size (kbytes/ kwords) (x8) address range (x16) address range bank 1 sa0 0000000000 8/4 000000h?001fffh 00000h?00fffh sa1 0000000001 8/4 002000h?003fffh 01000h?01fffh sa2 0000000010 8/4 004000h?005fffh 02000h?02fffh sa3 0000000011 8/4 006000h?007fffh 03000h?03fffh sa4 0000000100 8/4 008000h?009fffh 04000h?04fffh sa5 0000000101 8/4 00a000h?00bfffh 05000h?05fffh sa6 0000000110 8/4 00c000h?00dfffh 06000h?06fffh sa7 0000000111 8/4 00e000h?00ffffh 07000h?07fffh sa8 0000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa9 0000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa10 0000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa11 0000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa12 0000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa13 0000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa14 0000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa15 0001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa16 0001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa17 0001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa18 0001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa19 0001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa20 0001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa21 0001110xxx 64/32 0e0000h?0effffh 70000h?77fffh sa22 0001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh
12 s29jl064h s29jl064ha1 may 7, 2004 preliminary bank 2 sa23 0010000xxx 64/32 100000h?10ffffh 80000h?87fffh sa24 0010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa25 0010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa26 0010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa27 0010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa28 0010101xxx 64/32 150000h?15ffffh a8000h?affffh sa29 0010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa30 0010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa31 0011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa32 0011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa33 0011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa34 0011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa35 0011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa36 0011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa37 0011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa38 0011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa39 0100000xxx 64/32 200000h?20ffffh 100000h?107fffh sa40 0100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa41 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa42 0101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa43 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa44 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa45 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa46 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa47 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa48 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa49 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa50 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa51 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa52 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa53 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa54 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa55 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa56 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa57 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa58 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa59 0110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa60 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa61 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa62 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa63 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa64 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa65 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa66 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa67 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa68 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa69 0111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa70 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh table 2. s29jl064h sector architecture (continued) bank sector sector address a21?a12 sector size (kbytes/ kwords) (x8) address range (x16) address range
may 7, 2004 s29jl064ha1 s29jl064h 13 preliminary bank 3 sa71 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa72 1000001xxx 64/32 410000h?41ffffh 208000h?20ffffh sa73 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa74 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh sa75 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa76 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh sa77 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh sa78 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh sa79 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa80 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa81 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa82 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa83 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh sa84 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa85 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh sa86 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh sa87 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh sa88 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa89 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa90 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa91 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa92 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa93 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa94 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh sa95 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa96 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa97 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa98 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa99 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa100 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa101 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2fffffh sa102 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa103 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa104 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa105 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa106 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa107 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa108 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh sa109 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa110 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh sa111 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa112 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh sa113 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh sa114 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh sa115 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh sa116 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh sa117 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa118 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh table 2. s29jl064h sector architecture (continued) bank sector sector address a21?a12 sector size (kbytes/ kwords) (x8) address range (x16) address range
14 s29jl064h s29jl064ha1 may 7, 2004 preliminary note: the address range is a21:a-1 in byte mode (byte#=v il ) or a21:a0 in word mode (byte#=v ih ). table 3. bank address table 4. secsi tm sector addresses autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. bank 4 sa119 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa120 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa121 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa122 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh sa123 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa124 1110101xxx 64/32 750000h?75ffffh 3a8000h?3affffh sa125 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa126 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa127 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa128 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa129 1111010xxx 64/32 7a0000h?7affffh 3d0000h?3d7fffh sa130 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa131 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa132 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa133 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa134 1111111000 8/4 7f0000h?7f1fffh 3f8000h?3f8fffh sa135 1111111001 8/4 7f2000h?7f3fffh 3f9000h?3f9fffh sa136 1111111010 8/4 7f4000h?7f5fffh 3fa000h?3fafffh sa137 1111111011 8/4 7f6000h?7f7fffh 3fb000h?3fbfffh sa138 1111111100 8/4 7f8000h?7f9fffh 3fc000h?3fcfffh sa139 1111111101 8/4 7fa000h?7fbfffh 3fd000h?3fdfffh sa140 1111111110 8/4 7fc000h?7fdfffh 3fe000h?3fefffh sa141 1111111111 8/4 7fe000h?7fffffh 3ff000h?3fffffh bank a21?a19 1 000 2 001, 010, 011 3 100, 101, 110 4 111 device sector size (x8) address range (x16) address range s29jl064h 256 bytes 000000h?0000ffh 000000h?00007fh table 2. s29jl064h sector architecture (continued) bank sector sector address a21?a12 sector size (kbytes/ kwords) (x8) address range (x16) address range
may 7, 2004 s29jl064ha1 s29jl064h 15 preliminary sector/sector block protection and unprotection (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see ta b l e 5 ). the hardware sector protection feature disables both program and erase opera - tions in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector protection/ unprotection can be implemented via two methods. ta b l e 5 . s29jl064h boot sector/sector block addresses for protection/unprotection sector a21?a12 sector/ sector block size sa0 0000000000 8 kbytes sa1 0000000001 8 kbytes sa2 0000000010 8 kbytes sa3 0000000011 8 kbytes sa4 0000000100 8 kbytes sa5 0000000101 8 kbytes sa6 0000000110 8 kbytes sa7 0000000111 8 kbytes sa8?sa10 0000001xxx, 0000010xxx, 0000011xxx, 192 (3x64) kbytes sa11?sa14 00001xxxxx 256 (4x64) kbytes sa15?sa18 00010xxxxx 256 (4x64) kbytes sa19?sa22 00011xxxxx 256 (4x64) kbytes sa23?sa26 00100xxxxx 256 (4x64) kbytes sa27-sa30 00101xxxxx 256 (4x64) kbytes sa31-sa34 00110xxxxx 256 (4x64) kbytes sa35-sa38 00111xxxxx 256 (4x64) kbytes sa39-sa42 01000xxxxx 256 (4x64) kbytes sa43-sa46 01001xxxxx 256 (4x64) kbytes sa47-sa50 01010xxxxx 256 (4x64) kbytes sa51-sa54 01011xxxxx 256 (4x64) kbytes sa55?sa58 01100xxxxx 256 (4x64) kbytes sa59?sa62 01101xxxxx 256 (4x64) kbytes sa63?sa66 01110xxxxx 256 (4x64) kbytes sa67?sa70 01111xxxxx 256 (4x64) kbytes sa71?sa74 10000xxxxx 256 (4x64) kbytes sa75?sa78 10001xxxxx 256 (4x64) kbytes sa79?sa82 10010xxxxx 256 (4x64) kbytes sa83?sa86 10011xxxxx 256 (4x64) kbytes sa87?sa90 10100xxxxx 256 (4x64) kbytes sa91?sa94 10101xxxxx 256 (4x64) kbytes sa95?sa98 10110xxxxx 256 (4x64) kbytes sa99?sa102 10111xxxxx 256 (4x64) kbytes sa103?sa106 11000xxxxx 256 (4x64) kbytes sa107?sa110 11001xxxxx 256 (4x64) kbytes
16 s29jl064h s29jl064ha1 may 7, 2004 preliminary sa111?sa114 11010xxxxx 256 (4x64) kbytes sa115?sa118 11011xxxxx 256 (4x64) kbytes sa119?sa122 11100xxxxx 256 (4x64) kbytes sa123?sa126 11101xxxxx 256 (4x64) kbytes sa127?sa130 11110xxxxx 256 (4x64) kbytes sa131?sa133 1111100xxx, 1111101xxx, 1111110xxx 192 (3x64) kbytes sa134 1111111000 8 kbytes sa135 1111111001 8 kbytes sa136 1111111010 8 kbytes sa137 1111111011 8 kbytes sa138 1111111100 8 kbytes sa139 1111111101 8 kbytes sa140 1111111110 8 kbytes sa141 1111111111 8 kbytes sector a21?a12 sector/ sector block size
may 7, 2004 s29jl064ha1 s29jl064h 17 preliminary sector protect/sector unprotect requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithms and figure 26 shows the timing diagram. for sector unprotect, all unprotected sectors must first be protec ted prior to the first sector unprotect write cycle. note that the sector unprotect algorithm unprotects all sectors in par - allel. all previously protected sectors must be individually re-protected. to change data in protected sectors efficiently, the temporary sector unprotect func - tion is available. see ?temporary sector unprotect? . the device is shipped with all sectors unprotected. optional spansion program - ming service enable programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a sector is protected or unprotected. see the autoselect mode section for details. write protect (wp#) the write protect function provides a hardware method of protecting without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in sectors 0, 1, 140, and 141, independently of whether those sectors were protected or unprotected using the method described in ?sector/ sector block protection and unprotection? . if the system asserts v ih on the wp#/acc pin, the device reverts to whether sec - tors 0, 1, 140, and 141 were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in ?sector/sector block protection and unprotection? . note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. ta b l e 6 . wp#/acc modes temporary sector unprotect (note: for the following discussion, the term ?sector? applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see ta b l e 5 ). this feature allows temporary unprotection of previously protected sectors to change data in-system. the temporary sector unprotect mode is activated by setting the reset# pin to vid . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. shows the algorithm, and 25 shows the timing diagrams, for this feature. if the wp#/acc pin is at v il , sectors 0, 1, 140, and 141 will remain protected during the temporary sector unprotect mode. wp# input voltage device mode v il disables programming and erasing in sa0, sa1, sa140, and sa141 v ih enables programming and erasing in sa0, sa1, sa140, and sa141, dependent on whether they were last protected or unprotected. v hh enables accelerated progamming (acc). see ?accelerated program operation? on page 8. .
18 s29jl064h s29jl064ha1 may 7, 2004 preliminary . figure 1. temporary sector unprotect operation start perform erase or program operations reset# = v ih te m p o ra r y s e c t o r unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected (if wp#/acc = v il , sectors 0, 1, 140, and 141 will remain protected). 2. all previously protected sectors are protected once again.
may 7, 2004 s29jl064ha1 s29jl064h 19 preliminary figure 2. in-system sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 ms first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 ms data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
20 s29jl064h s29jl064ha1 may 7, 2004 preliminary secsi? (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 256 bytes in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. the product is available with the secsi sector either factory locked or customer lockable. the factory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? the customer-lockable version is shipped with the secsi sector unpro - tected, allowing customers to utilize the that sector in any manner they choose. the customer-lockable version has the secsi (secured silicon) sector indicator bit permanently set to a ?0.? thus, the secsi sector indicator bit prevents cus - tomer-lockable devices from being used to replace devices that are factory locked. the secsi customer indicator bit (dq6) is permanently set to 1 if the part has been customer locked, permanently se t to 0 if the part has been factory locked, and is 0 if customer lockable. the system accesses the secsi sector secure through a command sequence (see ?enter secsi? sector/exit secsi sector command sequence? ). after the system has written the enter secsi sector command sequence, it may read the secsi sector by using the addresses normally oc cupied by the boot sectors. this mode of operation continues until the system issues the exit secsi sector command se - quence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the first 256 bytes of sector 0. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. factory locked: secsi sector programmed and protected at the factory in a factory locked device, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. the device is preprogrammed with both a random number and a secure esn. the 8- word random number is at addresses 000000h?000007h in word mode (or 000000h?00000fh in byte mode). the secure esn is programmed in the next 8 words at addresses 000008h?00000fh (or 000010h?00001fh in byte mode). the device is available preprogram med with one of the following: ? a random, secure esn only ? customer code through spansion programming services ? both a random, secure esn and customer code through spansion program - ming services contact an your local sales office for details on using spansion programming services. customer lockable: secsi sector not programmed or protected at the factory if the security feature is not required, the secsi sector can be treated as an ad - ditional flash memory space. the secsi sector can be read any number of times, but can be programmed and locked only once. note that the accelerated pro - gramming (acc) and unlock bypass functions are not available when programming the secsi sector.
may 7, 2004 s29jl064ha1 s29jl064h 21 preliminary the secsi sector area can be protected using one of the following procedures: ? write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2 , ex - cept that reset# may be at either v ih or v id . this allows in-system protec - tion of the secsi sector region without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. ? to verify the protect/unprotect status of the secsi sector, follow the algo - rithm shown in figure 3 . once the secsi sector is locked and verified, the system must write the exit secsi sector region command sequence to retu rn to reading and writing the remainder of the array. the secsi sector lock must be used with caution since, once locked, there is no procedure available for unlocking the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. figure 3. secsi sector protect verify hardware data protection the command sequence requirement of unl ock cycles for programming or erasing provides data protection against inadvertent writes (refer to ta b l e 4 for command definitions). in addition, the following hardware data protection measures pre - vent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro - tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 ms read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
22 s29jl064h s29jl064ha1 may 7, 2004 preliminary mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft - ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back - ward-compatible for the specified flas h device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mo de (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 1 ? 3 . to terminate reading cfi data, the system must write the reset command.the cfi query mode is not accessible when the device is executing an embedded program or embedded erase algorithm. the system can also write the cfi query command when the device is in the au - toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 1 ? 3 . the system must write the reset command to reading array data. for further information, please refer to the cfi specification and cfi publication 100. contact your local sales office for copies of these documents.
may 7, 2004 s29jl064ha1 s29jl064h 23 preliminary ta b l e 1 . cfi query identification string table 7. system interface string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0003h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 0009h typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
24 s29jl064h s29jl064ha1 may 7, 2004 preliminary ta b l e 2 . device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0017h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0003h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 007dh 0000h 0000h 0001h erase block region 2 information (refer to the cfi specification or cfi publication 100) 35h 36h 37h 38h 6ah 6ch 6eh 70h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100)
may 7, 2004 s29jl064ha1 s29jl064h 25 preliminary ta b l e 3 . primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii (reflects modifications to the silicon) 44h 88h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h 8ah 000ch address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 01 =29f040 mode, 02 = 29f016 mode, 03 = 29f400, 04 = 29lv800 mode 4ah 94h 0077h simultaneous operation 00 = not supported, x = number of sectors (excluding bank 1) 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 0001h top/bottom boot sector flag 00h = uniform device, 01h = 8 x 8 kbyte sectors, top and bottom boot with write protect, 02h = bottom boot device, 03h = top boot device, 04h= both top and bottom 50h a0h 0001h program suspend 0 = not supported, 1 = supported 57h aeh 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h b0h 0017h bank 1 region information x = number of sectors in bank 1 59h b2h 0030h bank 2 region information x = number of sectors in bank 2 5ah b4h 0030h bank 3 region information x = number of sectors in bank 3 5bh b6h 0017h bank 4 region information x = number of sectors in bank 4
26 s29jl064h s29jl064ha1 may 7, 2004 preliminary command definitions writing specific address and data commands or sequences into the command register initiates device operations. ta b l e 4 defines the valid register command sequences. writing incorrect address and data values or writing them in the im - proper sequence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. the system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase re - sume commands section for more information. the system must issue the reset command to return a bank to the read (or erase- suspend-read) mode if dq5 goes high during an active program or erase opera - tion, or if the bank is in the autoselect mode. see the next section, reset command , for more information. see also requirements for reading array data in the device bus operations sec - tion for more information. the read-only operations table provides the read parameters, and 14 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys - tem was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to the read mode . if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-suspen d-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode.
may 7, 2004 s29jl064ha1 s29jl064h 27 preliminary if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manu - facturer and device codes, and determine whether or not a sector is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively programming or erasing in another bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the au - toselect command. the bank then enters the autoselect mode. the system may read any number of autoselect codes without reinitiating the command sequence. ta b l e 4 shows the address and data requirements. to determine sector protection information, the system must write to the appropriate bank address (ba) and sector address (sa). ta b l e 3 shows the address range and bank number associ - ated with each sector. the system must write the reset command to return to the read mode (or erase- suspend-read mode if the bank was previously in erase suspend). enter secsi? sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing a random, six - teen-byte electronic serial number (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector com - mand sequence returns the device to normal operation. the secsi sector is not accessible when the device is executing an embedded program or embedded erase algorithm. ta b l e 4 shows the address and data requirements for both com - mand sequences. see also ?secsi? (secured silicon) sector flash memory region? for further information. note that the acc function and un - lock bypass modes are not available when the secsi sector is enabled. byte/word program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. programming is a four-bus-cycle operation. the program com - mand sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. tab l e 4 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/by#. refer to the write operation status section for information on these status bits.
28 s29jl064h s29jl064ha1 may 7, 2004 preliminary any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. note that the secsi sec - tor, autoselect, and cfi functions are unavailable when a program operation is in progress. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard progra m command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program com - mand sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and da ta. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program - ming time. ta b l e 4 shows the requirements for the command sequence. during the unlock bypass mode, only th e unlock bypass program and unlock by - pass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (see table 12). the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en - ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh for any operation other than accelerated programming, or device dam - age may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result . 4 illustrates the algorithm for the program operation. refer to the erase and pro - gram operations table in the ac characteristics section for parameters, and figure 18 for timing diagrams.
may 7, 2004 s29jl064ha1 s29jl064h 29 preliminary figure 4. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini - tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto - matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim - ings during these operations. ta b l e 4 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase operation is in progress. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 4 for program command sequence.
30 s29jl064h s29jl064ha1 may 7, 2004 preliminary 5 illustrates the algorithm for the erase operation. refer to the erase and program operations tables in the ac characteristics section for parameters, and figure 20 section for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi - tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. ta b l e 4 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em - bedded erase algorithm automatically programs and verifies the entire sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 80 s occurs. during the time-out period, additional sector addresses and sector erase com - mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 80 s, otherwise erasure may begin. any sector erase address and command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure al l commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any com - mand other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system must rewrite the com - mand sequence and any additional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris - ing edge of the final we# or ce# pulse (first rising edge) in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading dq7, dq6, dq2, or ry/by# in the erasing bank. refer to the write operation sta - tus section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im - mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated on ce that bank has returned to reading array data, to ensure data integrity. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase operation is in progress. 5 illustrates the algorithm for the erase operation. refer to the erase and program operations tables in the ac characteristics section for parameters, and figure 20 section for timing diagrams.
may 7, 2004 s29jl064ha1 s29jl064h 31 preliminary figure 5. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this com - mand is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. the bank address must contain one of the sectors currently selected for erase. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. how - ever, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the erase-sus - pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta - tus information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 4 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
32 s29jl064h s29jl064ha1 may 7, 2004 preliminary after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard byte program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect com - mand sequence. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. refer to the autoselect mode and autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase- suspended bank is required when writ - ing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing.
may 7, 2004 s29jl064ha1 s29jl064h 33 preliminary ta b l e 4 . s29jl064h command definitions command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 (ba)555 90 (ba)x00 01 byte aaa 555 (ba)aaa device id (note 9) word 6 555 aa 2aa 55 (ba)555 90 (ba)x01 7e (ba)x0e 02 (ba)x0f 01 byte aaa 555 (ba)aaa (ba)x02 (ba)x1c (ba)x1e secsi sector factory protect (note 10) word 4 555 aa 2aa 55 (ba)555 90 (ba)x03 80/ 00 byte aaa 555 (ba)aaa (ba)x06 sector/sector block protect verify (note 11) word 4 555 aa 2aa 55 (ba)555 90 (sa)x02 00/ 01 byte aaa 555 (ba)aaa (sa)x04 enter secsi sector region word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit secsi sector region word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 12) 2 xxx a0 pa pd unlock bypass reset (note 13) 2 xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 14) 1 ba b0 erase resume (note 15) 1 ba 30 cfi query (note 16) word 1 55 98 byte aa l egend: x = don?t care r a = address of the memory location to be read. r d = data read from location ra during read operation. p a = address of the memory location to be programmed. addresses l atch on the falling edge of the we# or ce# pulse, whichever happens l ater. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a21?a12 uniquely select any sector. refer to table 3 for information on sector addresses. ba = address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased. a21?a19 uniquely select a bank. n otes: 1. see table 1 for description of bus operations. 2 . all values are in hexadecimal. 3 . except for the read cycle and the fourth, fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles. 4 . data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5 . unless otherwise noted, address bits a21?a11 are don?t cares for unlock and command cycles, unless sa or pa is required. 6 . no unlock or command cycles required when bank is reading array data. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information). 8 . the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the manufacturer id, device id, or secsi sector factory protect information. data bits dq15?dq8 are don?t care. while reading the autoselect addresses, the bank address must be the same until a reset command is given. see the autoselect command sequence section for more information. 9. the device id must be read across the fourth, fifth, and sixth cycles. 10. the data is 80h for factory locked, 40h for customer locked, and 00h for not factory/customer locked. 11. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. the unlock bypass command is required prior to the unlock bypass program command. 13. the unlock bypass reset command is required to return to the read mode when the bank is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. command is valid when device is ready to read array data or when device is in autoselect mode.
34 s29jl064h s29jl064ha1 may 7, 2004 preliminary write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. ta b l e 8 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for deter - mining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the com - plement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro - gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status in - formation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the bank returns to the read mode. if not all selected sectors are protected, the em - bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq15?dq0 (or dq7?dq0 for x8-only device) on the fol - lowing read cycles. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq15?dq8 (dq7?dq0 for x8- only device) while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq15?dq0 may be still invalid. valid data on dq15?dq0 (or dq7?dq0 for x8-only device) will appear on successive read cycles. ta b l e 8 shows the outputs for data# polling on dq7. 6 shows the data# polling algorithm. 22 in the ac characteristics section shows the data# polling timing diagram.
may 7, 2004 s29jl064ha1 s29jl064h 35 preliminary figure 6. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
36 s29jl064h s29jl064ha1 may 7, 2004 preliminary ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the stan dby mode, or one of the banks is in the erase-suspend-read mode. ta b l e 8 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy - cles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo - rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac - tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en - ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter - natively, the system can use dq7 (see the subsection on dq7: data# polling ). if a program address falls within a protected sector, dq6 toggles for approxi - mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete.
may 7, 2004 s29jl064ha1 s29jl064h 37 preliminary figure 7. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
38 s29jl064h s29jl064ha1 may 7, 2004 preliminary dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 8 to compare outputs for dq2 and dq6. 7 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsection. 23 shows the toggle bit timing diagram. 24 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to 7 for the following discussion. whenever the system initially begins read - ing toggle bit status, it must read dq15?dq0 (or dq7?dq0 for x8-only device) at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq15?dq0 (or dq7?dq0 for x8-only device) on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc - cessfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de - scribed in the previous paragraph. altern atively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo - rithm when it returns to determine the status of the operation (top of 7 ). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified in - ternal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the opera - tion, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspen d-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de - termine whether or not erasure has begun. (the sector erase timer does not
may 7, 2004 s29jl064ha1 s29jl064h 39 preliminary apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be as - sumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept addi - tional sector erase commands. to ensu re the command has been accepted, the system software should check the status of dq3 prior to and following each sub - sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 8 shows the status of dq3 relative to the other status bits. table 8. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status in formation. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
40 s29jl064h s29jl064ha1 may 7, 2004 preliminary absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?65c to +125c voltage with respect to ground v cc (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v oe# and reset# (note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v wp#/acc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +10.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ? 2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 8 . during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 9 . 2. minimum dc input voltage on pins oe#, reset#, and wp#/acc is ?0.5 v. during voltage transitions, oe#, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8 . maximum dc input voltage on wp#/ acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges wireless (w) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?25c to +85c industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c v cc supply voltages v cc for standard voltage range . . . . . . . . . . . . . . . . . . . . . . . . 2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed. figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
may 7, 2004 s29jl064ha1 s29jl064h 41 preliminary dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 5. not 100% tested. paramete r symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit oe# and reset# input load current v cc = v cc max , oe# = v ih ; oe# or reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max , oe# = v ih 1.0 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i cc1 v cc active read current (notes 1 , 2 ) ce# = v il , oe# = v ih , byte mode 5 mhz 10 16 ma 1 mhz 2 4 ce# = v il , oe# = v ih , word mode 5 mhz 10 16 1 mhz 2 4 i cc2 v cc active write current (notes 2 , 3 ) ce# = v il , oe# = v ih , we# = v il 15 30 ma i cc3 v cc standby current (note 2) ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc reset current (note 2) reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (notes 2 , 4 ) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a i cc6 v cc active read-while-program current (notes 1 , 2 ) ce# = v il , oe# = v ih byte 21 45 ma word 21 45 i cc7 v cc active read-while-erase current (notes 1 , 2 ) ce# = v il , oe# = v ih byte 21 45 ma word 21 45 i cc8 v cc active program-while-erase- suspended current (notes 2 , 5 ) ce# = v il , oe# = v ih 17 35 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v hh voltage for wp#/acc sector protect/unprotect and program acceleration v cc = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 2.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage (note 5) 2.3 2.5 v
42 s29jl064h s29jl064ha1 may 7, 2004 preliminary dc characteristics zero-power flash note: addresses are switching at 1 mhz figure 10. i cc1 current vs. time (showing active and automatic sleep currents) 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 1 2345 frequency in mhz supply current in ma note: t = 25 c figure 11. ty p i c a l i cc1 vs. frequency 2.7 v 3.6 v 4 6 12
may 7, 2004 s29jl064ha1 s29jl064h 43 preliminary test conditions table 5. test specifications key to switching waveforms test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v 2.7 k ? c l 6.2 k ? 3.3 v device under te s t note: diodes are in3064 or equivalent figure 12. test setup waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 13. input waveforms and measurement levels
44 s29jl064h s29jl064ha1 may 7, 2004 preliminary ac characteristics read-only operations notes: 1. not 100% tested. 2. see 12 and table 5 for test specifications 3. measurements performed by placing a 50 ohm termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . parameter description test setup speed options jedec std. 55 70 85 unit t avav t rc read cycle time (note 1) min 55 70 85 ns t avqv t acc address to output delay ce#, oe# = v il max 55 70 85 ns t elqv t ce chip enable to output delay oe# = v il max 55 70 85 ns t glqv t oe output enable to output delay max 25 30 40 ns t ehqz t df chip enable to output high z (notes 1 , 3 ) max 16 ns t ghqz t df output enable to output high z (notes 1 , 3 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 5 10 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df figure 14. read operation timings
may 7, 2004 s29jl064ha1 s29jl064h 45 preliminary ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb figure 15. reset timings
46 s29jl064h s29jl064ha1 may 7, 2004 preliminary ac characteristics word/byte configuration (byte#) parameter speed options jedec std. description 55 70 85 unit t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 16 ns t fhqv byte# switching high to output active min 55 70 85 ns
may 7, 2004 s29jl064ha1 s29jl064h 47 preliminary dq15 output data output (dq7?dq0) ce# oe# byte# t elfl dq14?dq0 data output (dq14?dq0) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq7?dq0) byte# t elfh dq14?dq0 data output (dq14?dq0) dq15/a-1 address input t fhqv byte# switching from byte to word mode figure 16. byte# timings for read operations note: refer to the erase/program operations table for t as and t ah specifications. figure 17. byte# timings for write operations ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
48 s29jl064h s29jl064ha1 may 7, 2004 preliminary ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed options jedec std description 55 70 85 unit t avav t wc write cycle time (note 1) min 55 70 85 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 30 40 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 40 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 25 30 35 ns t whdl t wph write pulse width high min 25 30 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) byte typ 5 s word typ 7 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.4 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns
may 7, 2004 s29jl064ha1 s29jl064h 49 preliminary ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. figure 18. program operation timings wp#/acc t vhh v hh v il or v ih v il or v ih t vhh figure 19. accelerated program timing diagram
50 s29jl064h s29jl064ha1 may 7, 2004 preliminary ac characteristics oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy n otes: 1. sa = sector address (for sector er ase), va = valid address for reading status data (see ?write operation status?. 2 . these waveforms are for the word mode. figure 20. chip/sector erase operation timings
may 7, 2004 s29jl064ha1 s29jl064h 51 preliminary ac characteristics oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce# or ce2# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w figure 21. back-to-back read/write cycle timings we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 22. data# polling timings (during embedded algorithms)
52 s29jl064h s29jl064ha1 may 7, 2004 preliminary ac characteristics oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle figure 23. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 24. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
may 7, 2004 s29jl064ha1 s29jl064h 53 preliminary ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 25. temporary sector unprotect timing diagram
54 s29jl064h s29jl064ha1 may 7, 2004 preliminary ac characteristics sector group protect: 150 s sector group unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. figure 26. sector/sector block protect and unprotect timing diagram
may 7, 2004 s29jl064ha1 s29jl064h 55 preliminary ac characteristics alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. parameter speed options jedec std. description 55 70 85 unit t avav t wc write cycle time (note 1) min 55 70 85 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 30 40 45 ns t dveh t ds data setup time min 30 40 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 40 45 ns t ehel t cph ce# pulse width high min 25 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 5 s word typ 7 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.4 sec
56 s29jl064h s29jl064ha1 may 7, 2004 preliminary ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. figure 27. alternate ce# controlled write (erase/program) operation timings
may 7, 2004 s29jl064ha1 s29jl064h 57 preliminary erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 100,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 4 for further information on command definitions. 6. the device has a minimum cycling endurance of 100,000 cycles per sector. parameter typ (note 1) max (note 2) unit comments sector erase time 0.4 5 sec excludes 00h programming prior to erasure (note 4) chip erase time 56 sec word program time 7 210 s excludes system level overhead (note 5) accelerated byte/word program time 4 120 s accelerated chip programming time 10 30 sec byte program time 5 150 s chip program time (note 3) byte mode 42 126 sec word mode 28 84
58 s29jl064h s29jl064ha1 may 7, 2004 preliminary
february 25, 2004 sram_samsung_01a2 16 mb sram (supplier 1) 59 preliminary 16 mb sram (supplier 1) 16 megabit (1mb x 16 bit) cmos sram functional description note: x means don?t care (must be low or high state). absolute maximum ratings stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional operation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect reliability . ce1# cs2 oe# we# lb# ub# io 0~7 io 8~15 mode power h x x x x x high-z high-z deselected standby x l x x x x high-z high-z deselected standby x x x x h h high-z high-z deselected standby l h h h l x high-z high-z output disabled active l h h h x l high-z high-z output disabled active l h l h l h d out high-z lower byte read active l h l h h l high-z d out upper byte read active l h l h l l d out d out word read active l h x l l h d in high-z lower byte write active l h x l h l high-z d in upper byte write active l h x l l l d in d in word write active item symbol ratings unit voltage on any pin relative to v ss v in ,v out -0.2 to v cc +0.3v (max. 3.6v) v voltage on v cc supply relative to v ss v cc -0.2 to 3.6v v power dissipation p d 1.0 w storage temperature t stg -85 to 150 c operating temperature t a -40 to 85 c
60 16 mb sram (supplier 1) sram_samsung_01a2 february 25, 2004 preliminary dc characteristics recommended dc operating conditions (note 1) notes: 1. t a = -40 to 85 c, otherwise specified. 2. overshoot: vcc+2.0v in case of pulse width 20ns. 3. undershoot: -2.0v in case of pulse width 20ns. 4. overshoot and undershoot are sampled, not 100% tested. capacitance (f=1mhz, t a =25 c) note: capacitance is sampled, not 100% tested dc operating characteristics note: typical values are measured at v cc =2.0v, t a =25 c and not 100% tested. item symbol min ty p max unit supply voltage v cc 2.7 3.0 3.3 v ground v ss 0 0 0 v input high voltage v ih 2.2 - v cc +0.2 (note 2) v input low voltage v il -0.2 (note 3) - 0.6 v item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf item symbol test conditions min ty p (note) max unit input leakage current i li v in =v ss to v cc -1 - 1 a output leakage current i lo ce1#=v ih , cs2=v il or oe#=v ih or we#=v il or lb#=ub#=v ih , v io =v ss to v cc -1 - 1 a average operating current i cc1 cycle time=1 s, 100% duty, i io =0ma, ce1# 0.2v, lb# 0.2v and/or ub# 0.2v, cs2 v cc -0.2v, v in 0.2v or v in v cc -0.2v - - 5 a i cc2 cycle time=min, i io =0ma, 100% duty, ce1#=v il , cs2=v ih , lb#=v il and/or ub#=v il , v in =v il or v ih 70ns - - 30 ma output low voltage v ol i ol = 2.1ma - - 0.4 v output high voltage v oh i oh = -1.0ma 2.4 - - v standby current (cmos) i sb1 other input = 0-v cc 1. ce1# v cc -0.2v, cs2 v cc -0.2v (ce1# controlled) or 2. 0v cs2 0.2v (cs2 controlled) - -5.0 25 a
february 25, 2004 sram_samsung_01a2 16 mb sram (supplier 1) 61 preliminary ac characteristics read/write charcteristics (v cc =2.7-3.3v) data retention characteristics notes: 1. ce1# vcc-0.2, cs2 vcc-0.2v (ce1# controlled) or 0 cs2-0.2v (cs2 controlled) 2. typical values are measured at t a =26 c and not 100% tested. parameter list symbol min max units read read cycle time t rc 70 - ns address access time t aa - 70 ns chip select to output t co1 , t co2 - 70 ns output enable to valid output t oe - 35 ns lb#, ub# valid to data output t ba - 70 ns chip select to low-z output t lz1 , t lz2 10 - ns output enable to low-z output t olz 5 - ns lb#, ub# enable to low-z output t blz 10 - ns output hold from address change t oh 10 - ns chip disable to high-z output t hz1 , t hz2 0 25 ns oe# disable to high-z output t ohz 0 25 ns ub#, lb# disable to high-z output t bhz 0 25 ns write write cycle time t wc 70 - ns chip select to end of write t cw1 , t cw2 60 - ns address set-up time t as 0 - ns address valid to end of write t aw 60 - ns write pulse width t wp 50 - ns write recovery time t wr 0 - ns write to output high-z t whz 0 20 ns data to write time overlap t dw 30 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns lb#, ub# valid to end of write t bw 60 - ns item symbol test condition min ty p max unit v cc for data retention v dr ce1# v cc -0.2v (note 1) , v in 0v 1.5 - 3.3 v data retention current i dr v cc =1.5v, ce1# v-0.2v (note 1) , v in 0v - 1.0 (note 2) 15 a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - -
62 16 mb sram (supplier 1) sram_samsung_01a2 february 25, 2004 preliminary timing diagrams figure 28. timing waveform of read cycle(1) (address controlled, cd#1=oe#=v il , cs2=we#=v ih , ub# and/or lb#=v il ) notes: 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. figure 29. timing waveform of read cycle(2) (we#=v ih ) address data out previous data valid data valid t aa t rc t oh data valid high-z t rc address data out t oh t aa t co1 t ba t oe t olz t blz t lz t ohz t bhz t hz cs2 t co2 cs1# ub#, lb# oe#
february 25, 2004 sram_samsung_01a2 16 mb sram (supplier 1) 63 preliminary figure 30. timing waveform of write cycle(1) (we# controlled) figure 31. timing waveform of write cycle(2) (cs# controlled) address data undefined data in data out t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs2 cs1# ub#, lb# we# address data valid data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) t as(3) cs1# cs 2 ub#, lb# we#
64 16 mb sram (supplier 1) sram_samsung_01a2 february 25, 2004 preliminary notes: 1. a write occurs during the overlap(t wp ) of low cs1# and low we#. a write begins when cs1# goes low and we# goes low with asserting ub# or lb# for single byte oper ation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs1# goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs1# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs1# or we# going high. figure 32. timing waveform of write cycle(3) (ub#, lb# controlled) address data valid data in data out high-z high-z t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs1# cs2 ub#, lb# we#
february 25, 2004 sram_samsung_01a2 16 mb sram (supplier 1) 65 preliminary figure 33. data retention waveform v cc 2.7v 2.2v v dr gnd data retention mode cs1# v cc - 0.2v, cs2 v cc -0.2v tsdr t rdr v cc 2.7v 0.4v v dr cs2 gnd data retention mode t sdr t rdr cs2 0.2v cs1# cs1# controlled cs2 controlled
66 16 mb sram (supplier 1) sram_samsung_01a2 february 25, 2004 preliminary
february 25, 2004 psram_nanoamp_03a2 8 mb psram (supplier 2) 67 preliminary 8 mb psram (supplier 2) 8 megabit (512 k x 16 bit) ultra-low power asynchronous cmos pseudo sram features ? single wide power supply range ? 2.7 to 3.6 volts ? very low standby current ? 65a at 3.0v (max) ? simple memory control ? dual chip enables (ce1# and ce2) ? byte control for independent byte operation ? output enable (oe#) for memory expansion ? very fast output enable access time ? 35ns oe# access time ? automatic power down to standby mode ? ttl compatible three-state output driver ? operating temperature ? -40c to +85c ? power supply ? 2.3v - 3.6v ? speed ? 70ns @ 2.7v general description the s71jl064h80?10/11/12 contains an integrated memory device containing a low power 8 mbit sram built using a self-refresh dram array organized as 512,288 words by 16 bits. it is designed to be identical in operation and interface to standard 6t srams. the device is designed for low standby and operating cur - rent and includes a power-down feature to automatically enter standby mode. the device operates with two chip enable (ce1# and ce2) controls and output enable (oe#) to allow for easy memory expansion. byte controls (ub# and lb#) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. the s71jl064h80 is optimal for various applications where low-power is critical such as battery backup and hand-held devices. the device can operate over a very wide temperature range of -40c to +85c and is available in tested wafer format.
68 8 mb psram (supplier 2) psram_nanoamp_03a2 february 25, 2004 preliminary block diagram notes: 1. when ub# and lb# are in select mode (low), i/o 0 - i/o 15 are affected as shown. when lb# only is in the select mode only i/o 0 - i/o 7 are affected as shown. when ub# is in the select mode only i/o 8 - i/o 15 are affected as shown. 2. when the device is in standby mode, control inputs (w e#, oe#, ub#, and lb#), address inputs and data input/ outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. when we# is invoked, the oe# input is internal ly disabled and has no effect on the circuit. absolute maximum ratings (see note) note: stresses greater than those listed above may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operating section of figure 34. functional block diagram ta b l e 9 . functional description ce1# ce2 we# oe# ub# lb# i/o 0 - i/o 15 (note 1) mode power h x x x x x high z standby (note 2) standby x l x x x x high z standby (note 2) standby l h x x h h high z standby standby l h l x (note 3) l (note 1) l (note 1) data in write active l h h l l (note 1) l (note 1) data out read active l h h h l (note 1) l (note 1) high z active active item symbol rating unit voltage on any pin relative to v ss v in,out ?0.3 to v cc +0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 4.5 v operating temperature t a -40 to +85 c address inputs a 0 - a 18 512k x 16 bit ram array input/ output mux and buffers address decode logic control logic i/o 0 - i/o 7 i/o 8 - i/o 15 ce1# ce2 we# oe# ub# lb#
february 25, 2004 psram_nanoamp_03a2 8 mb psram (supplier 2) 69 preliminary this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli - ability. dc characteristics operating characteristics (over specified temperature range) notes: 1. typical values are measured at v cc =v cc typ., ta=25c, and not 100% tested. 2. this parameter is specified with the outputs disabled to avoid external loading effects. the user must add current required to drive output capacitance expected in the actual system. ac characteristics item symbol test conditions min ty p . (note 1) max. unit supply voltage v cc 2.7 3.0 3.6 v input high voltage v ih 2.2 v cc +0.3 v input low voltage v il ?0.3 0.6 v output high voltage v oh i oh = -1.0ma v cc ?0.4 v output low voltage v ol i ol = 2.0ma 0.4 v input leakage current i li v in = 0 to v cc 0.5 a output leakage current i lo oe# = v ih or chip disabled 0.5 a read/write operating supply current @ 1 s cycle time (note 2) i cc1 v cc =3.6 v, v in =v ih or v il chip enabled, i out = 0 3.0 5.0 ma i cc2 v cc =3.3 v, v in =v ih or v il chip enabled, i out = 0 5.0 read/write operating supply current @ 70ns cycle time (note 2) i cc3 v cc =3.6 v, v in =v ih or v il chip enabled, i out = 0 12.0 25.0 ma i cc4 v cc =3.3 v, v in =v ih or v il chip enabled, i out = 0 23.0 maximum standby current (standard part) i sb1 v in = v cc or 0v chip disabled t a = 85 o c, v cc = 3.0 v 70.0 a maximum standby current (ultra low power part) i sb1 v in = v cc or 0v chip disabled t a = 85 o c, v cc = 3.0 v 60.0 a ta b l e 1 0 . timing test conditions item input pulse level 0.1v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc operating temperature -40 c to +85 c
70 8 mb psram (supplier 2) psram_nanoamp_03a2 february 25, 2004 preliminary ta b l e 1 1 . timings parameter list symbol speed bins unit 55 70 min. max. min. max. read cycle read cycle time t rc 55 70 ns address access time t aa 55 70 ns chip enable to valid output t co 55 70 ns output enable to valid output t oe 30 35 ns byte select to valid output t lb , t ub 55 70 ns chip enable to low-z output t lz 5 5 ns output enable to low-z output t olz 5 5 ns byte select to low-z output t lbz , t ubz 5 5 ns chip disable to high-z output t hz 0 20 0 25 ns output disable to high-z output t ohz 0 20 0 25 ns byte select disable to high-z output t lbhz , t ubhz 0 20 0 25 ns output hold from address change t oh 10 10 ns write cycle write cycle time t wc 55 70 ns chip enable to end of write t cw 45 55 ns address valid to end of write t aw 45 55 ns byte select to end of write t lbw , t ubw 45 55 ns write pulse width t wp 45 55 ns address setup time t as 0 0 ns write recovery time t wr 0 0 ns write to high-z output t whz 25 25 ns data to write time overlap t dw 40 40 ns data hold from write time t dh 0 0 ns end write to low-z output t ow 5 5 ns
february 25, 2004 psram_nanoamp_03a2 8 mb psram (supplier 2) 71 preliminary timing diagrams figure 35. timing of read cycle (ce1# = oe# = v il , we# = ce2 = v ih ) figure 36. timing waveform of read cycle (we# = v ih ) t rc t aa t oh data valid previous data valid address data out data valid t rc t aa t co t hz t ohz t lbhz, t ubhz t olz t oe t lz high-z t lb, t ub t lblz, t ublz address ce1# ce2 oe# lb#, ub data out
72 8 mb psram (supplier 2) psram_nanoamp_03a2 february 25, 2004 preliminary figure 37. timing waveform of write cycle (we# control) figure 38. timing waveform of write cycle (ce1# control) data valid t wc t aw t cw t wr t whz t dh high-z high-z t ow t as t wp t dw t lbw , t ubw address ce1# ce2 lb#, ub we# data in data out data valid t wc t aw t cw t wr t dh high-z t as t wp t lz t dw t lbw , t ubw t whz address ce1# lb#, ub we# data in data out (for ce2 control, use inverted signal
february 25, 2004 psram_nanoamp_02a2 16 mb psram (supplier 2) 73 preliminary 16 mb psram (supplier 2) 16 megabit (1mb x 16bit) ultra-low power asynchronous cmos pseudo sram features ? single wide power supply range ? 2.7 to 3.6 volts ? very low standby current ? 100a at 3.0v (max) ? simple memory control ? dual chip enables (ce1# and ce2) ? byte control for independent byte operation ? output enable (oe#) for memory expansion ? very fast access time ? 55ns address access option ? 35ns oe# access time ? automatic power down to standby mode ? ttl compatible three-state output driver ? operating temperature ? -40c to +85c ? speed ?70ns ?55 ns general description the s71jl064ha0-10/11/12 contains an integrated memory device containing a low-power, 16 mbit sram built using a self-refresh dram array organized as 1,024,576 words by 16 bits. it is designed to be identical in operation and inter - face to standard 6t srams. the device is designed for low standby and operating current and includes a power-down featur e to automatically enter standby mode. the device operates with two chip enable (ce1# and ce2) controls and output enable (oe#) to allow for easy memory expansion. byte controls (ub# and lb#) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. the s71jl064ha0 is optimal for various applications where low-power is critical, such as battery backup and hand-held devices. the device can operate over a very wide temperature range of -40c to +85c and is available in tested wafer format.
74 16 mb psram (supplier 2) psram_nanoamp_02a2 february 25, 2004 preliminary block diagram notes: 1. when ub# and lb# are in select mode (low), i/o 0 - i/o 15 are affected as shown. when lb# only is in the select mode only i/o 0 - io 7 are affected as shown. when ub is in the select mode only i/o 8 - i/o 15 are affected as shown. if both ub# and lb# are in the deselect mode (high), the chip is in a standby mode regardless of the state of ce1# or ce2.# 2. when the device is in standby mode, control inputs (w e#, oe#, ub#, and lb), address inputs and data input/ outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. when we# is invoked, the oe# input is internal ly disabled and has no effect on the circuit. 4. the device will consume active power in this mode when ever addresses are changed. data inputs are internally isolated from any external influence. figure 39. functional block diagram ta b l e 1 2 . functional description ce1# ce2 we# oe# ub#/lb# i/o ( note 1 ) mode power h x x x x high z standby ( note 2 ) standby x l x x x high z standby ( note 4 ) standby l h x x h high z standby ( note 4 ) standby l h l x l ( note 3 ) data in write ( note 3 ) active -> standby ( note 4 ) l h h l l ( note 3 ) data out read active -> standby ( note 4 ) l h h h l ( note 3 ) high z active standby ( note 4 ) address inputs a 0 - a 19 1024k x 16 bit ram array input/ output mux and buffers address decode logic control logic i/o 0 - i/o 7 i/o 8 - i/o 15 ce1# ce2 we# oe# ub# lb#
february 25, 2004 psram_nanoamp_02a2 16 mb psram (supplier 2) 75 preliminary absolute maximum ratings (see note) note: stresses greater than those listed above may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reli - ability. dc characteristics operating characteristics (over specified temperature range) notes: 1. typical values are measured at v cc =v cc typ., t a =25c, and not 100% tested. 2. this parameter is specified with the outputs disabled to avoid external loading effects. the user must add current required to drive output capacitance expected in the actual system. item symbol rating unit voltage on any pin relative to v ss v in,out ?0.3 to v cc +0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 4.0 v power dissipation p d 500 mw storage temperature t stg ?40 to 125 c operating temperature t a -40 to +85 c item symbol comments min ty p . ( note 1 ) max. unit supply voltage v cc 2.7 3.0 3.6 v input high voltage v ih 2.2 v cc +0.3 v input low voltage v il ?0.3 0.6 v output high voltage v oh i oh = -0.2 ma v cc -0.2 v output low voltage v ol i ol = 0.2 ma 0.2 v input leakage current i li v in = 0 to v cc 0.5 a output leakage current i lo oe# = v ih or chip disabled 0.5 a read/write operating supply current @ 1 s cycle time ( note 2 ) i cc1 v cc =v cc max, v in =v ih /v il chip enabled, i out = 0 5 ma read/write operating supply current @ min cycle time ( note 2 ) i cc2 v cc =v cc max, v in =v ih /v il chip enabled, i out = 0 25 ma standby current i sb v in = v cc or 0v chip disabled t a = 85c, v cc = 3.0v 100.0 a
76 16 mb psram (supplier 2) psram_nanoamp_02a2 february 25, 2004 preliminary ac characteristics timing test conditions timings item input pulse level 0.1 v cc to 0.9 v cc input rise and fall time 5ns input and output timing reference levels 0.5 v cc operating temperature -40 c to +85 c item symbol 55 70 unit min. max. min. max. read cycle time t rc 55 70 ns address access time t aa 55 70 ns chip enable to valid output t co 55 70 ns output enable to valid output t oe 30 35 ns byte select to valid output t lb , t ub 55 70 ns chip enable to low-z output t lz 5 5 ns output enable to low-z output t olz 5 5 ns byte select to low-z output t lbz , t ubz 5 5 ns chip disable to high-z output t hz 0 25 0 25 ns output disable to high-z output t ohz 0 25 0 25 ns byte select disable to high-z output t lbhz , t ubhz 0 25 0 25 ns output hold from address change t oh 10 10 ns write cycle time t wc 55 70 ns chip enable to end of write t cw 50 55 ns address valid to end of write t aw 50 55 ns byte select to end of write t lbw , t ubw 50 55 ns write pulse width t wp 50 55 ns write recovery time t wr 0 0 ns write to high-z output t whz 25 25 ns address setup time t as 0 0 ns data to write time overlap t dw 25 25 ns data hold from write time t dh 0 0 ns end write to low-z output t ow 5 5 ns
february 25, 2004 psram_nanoamp_02a2 16 mb psram (supplier 2) 77 preliminary timings figure 40. timing of read cycle (ce1# = oe# = v il , we# = ce2 = v ih ) figure 41. timing waveform of read cycle (we# = v ih ) address data out t rc t aa t oh data valid previous data valid address lb#, ub# oe# data valid t rc t aa t co t hz t ohz t lbhz , t ubhz t olz t oe t lz high-z data out t lb , t ub t lblz , t ublz ce1# ce2
78 16 mb psram (supplier 2) psram_nanoamp_02a2 february 25, 2004 preliminary figure 42. timing waveform of write cycle (we# control) figure 43. timing waveform of write cycle (ce1# control, ce2 = high) address d ata valid t wc t aw t cw t wr t whz t dh hi gh-z high- z t ow t as t wp t dw t lbw , t ubw data out data in we# lb#, ub# ce2 ce1# address t wc t aw t cw t wr t dh high- z t as t wp t dw t lbw , t ubw t whz ce1# lb#, ub# we# data in data out data valid
february 25, 2004 psram_etrontech_06a2 16 mb psram (supplier 4) 79 preliminary 16 mb psram (supplier 4) 16 megabit (1m x 16) cmos pseudo sram features ? organized as 1m words by 16 bits ? fast cycle time : 70 ns ? standby current : 100 a ? deep power-down current : 10 a (memory cell data invalid) ? byte data control: lb# (dq0 - 7), ub# (dq8 - 15) ? compatible with low-power sram ? single power supply voltage : 3.0v0.3v description the s71jl064ha0 model #62 contains a 16m-bit pseudo sram organized as 1m words by 16 bits. it is designed with advanced cmos technology specified ram featuring low-power static ram-compatible function and pin configuration. this device operates from a single power supply. advanced circuit technology provides both high speed and low power. it is automatically placed in low-power mode when cs1# or both ub# and lb# are asserted high or cs2 is asserted low. there are three control inputs. cs1# and cs2 are used to select the device, and output enable (oe#) provides fast memory access. data byte control pins (lb#,ub#) provide lower and upper byte access. this device is well suited to various micro - processor system applications where high speed, low power and battery backup are required. pin description a0 ? a19 = address inputs dq0 ? dq15 = data inputs/outputs ce1# = chip enable ce2 = deep power down oe# = output enable we# = write control lb# = lower byte control ub# = upper byte control vcc = power supply vss = ground
80 16 mb psram (supplier 4) psram_etrontech_06a2 february 25, 2004 preliminary operation mode note: x=don?t care. h=logic high. l=logic low. absolute maxumum ratings (see note) note: absolute maximum dc requirements contains stress ratings only. functional operation at the absolute maximum limits is not implied or guaranteed. extended exposure to maximum ratings may affect device reliability. dc characteristics notes: 1. overshoot: v cc + 2.0v in case of pulse width 20ns 2. undershoot: -2.0v in case of pulse width 20ns 3. overshoot and undershoot are sampled, not 100% tested. mode ce1# ce2 oe# we# lb# ub# dq0 to dq7 dq8 to dq15 power deselect h h x x x x high-z high-z standby deselect x l x x x x high-z high-z deep power down deselect l h x x h h high-z high-z standby output disabled l h h h l x high-z high-z active output disabled l h h h x l high-z high-z active lower byte read l h l h l h d-out high-z active upper byte read l h l h h l high-z d-out active word read l h l h l l d-out d-out active lower byte write l h x l l h d-in high-z active upper byte write l h x l h l high-z d-in active word write l h x l l l d-in d-in active symbol rating value unit v cc supply voltage -0.2 to +3.6 v v in input voltages -0.2 to v cc + 0.3 v v in , v out output and output voltages -2.0 to +3.6 v i sh output short circuit current 100 ma p d power dissipation 1 w ta b l e 1 3 . dc recommended operating conditions symbol pa r a m e t e r min typ. max unit v dd power supply voltage 2.7 3.0 3.3 v v ss ground 0 - 0 v ih input high voltage 2.2 - v cc + 0.2 ( note 1 ) v il input low voltage -0.2 ( note 2 ) - +0.6
february 25, 2004 psram_etrontech_06a2 16 mb psram (supplier 4) 81 preliminary ac characteristics ta b l e 1 4 . dc characteristics (t a = -25 c to 85 c, vdd = 2.6 to 3.3v) symbol param ete r test condition min max unit i il input leakage current v in = v ss to v dd -1 1 a i lo output leakage current v io = v ss to v dd ce1# = v ih , ce2 = v il or oe# = v ih or we# = v il -1 1 a i cc1 operating current @ min cycle time cycle time = min., 100% duty, i io = 0ma, ce1# = v il , ce2 = v ih , v in = v ih or v il - 35 ma i cc2 operating current @ max cycle time cycle time = 1 s, 100% duty i io = 0ma, ce1# 0.2v, ce2 v dd -0.2v, v in 0.2v or v in v dd -0.2v - 5 ma i sb1 standby current (cmos) ce1# = v dd ? 0.2v and ce2 = v dd ? 0.2v, other inputs = v ss ~ v cc - 100 a i sbd deep power-down ce2 0.2v, other inputs = v ss ~ v cc 10 a v ol output low voltage i ol = 2.1ma - 0.4 v v oh output high voltage i oh = -1.0ma 2.4 - v ta b l e 1 5 . ac characteristics and operating conditions (t a = -25 c to 85 c, v dd = 2.6 to 3.3v) cycle symbol parameter 70 unit min max read t rc read cycle time 70 - ns t aa address access time - 70 ns t co1 chip enable (ce#1) access time - 70 ns t co2 chip enable (ce2) access time - 70 ns t oe output enable access time - 35 ns t ba data byte control access time - 70 ns t lz chip enable low to output in low-z 10 - ns t olz output enable low to output in low-z 5 - ns t blz data byte control low to output in low-z 10 - ns t hz chip enable high to output in high-z - 25 ns t ohz output enable high to output in high-z - 25 ns t bhz data byte control high to output in high-z - 25 ns t oh output data hold time 10 - ns
82 16 mb psram (supplier 4) psram_etrontech_06a2 february 25, 2004 preliminary write t wc write cycle time 70 - ns t wp write pulse width 50 - ns t aw address valid to end of write 60 - ns t cw chip enable to end of write 60 - ns t bw data byte control to end of write 60 - ns t as address set-up time 0 - ns t wr write recovery time 0 - ns t wzh we# low to output high-z - 20 ns t ow we# high to output in high-z 5 - ns t dw data to write overlap 35 - ns t dh data hold time 0 - ns t weh we# high time 5 10 ns ta b l e 1 6 . ac test conditions parameter condition output load 50 pf + 1 ttl gate input pulse level 0.4 v, 2.4 timing measurements 0.5 v cc t r , t f 5 ns note: including scope and jig capacitance figure 44. ac test loads table 15. ac characteristics and operating conditions (t a = -25 c to 85 c, v dd = 2.6 to 3.3v) (continued) cycle symbol parameter 70 unit min max c l r l = 50 ? z 0 = 50 ? d out v l = 1.5 v = 50 pf (see note)
february 25, 2004 psram_etrontech_06a2 16 mb psram (supplier 4) 83 preliminary timing diagrams figure 45. state diagram ta b l e 1 7 . standby mode characteristics power mode memory cell data standby current (a) wait time (s) standby valid 100 0 deep power down invalid 10 200 note: ce1# = oe# = v il , ce2 = we# = v ih , ub# and/or lb# = v il figure 46. read cycle 1?addressed controlled ce2=vih ce2=v il ce1# = v ih or v il , ce2=v ih ce2=v il ce2=v ih , ce1# =v ih or ub#, lb# =v ih ce1# =v il , ce2=v ih , ub# & lb# or/and lb# = v il powe r on initial state (wait 200 s) e deep powe r down mode standby mode powe r up sequence deep pow er down exit sequence active deep power down entry sequence t rc t oh t oh previous data valid data valid t a a address data out
84 16 mb psram (supplier 4) psram_etrontech_06a2 february 25, 2004 preliminary note: ce2 = we# = v ih figure 47. read cycle 2?cs1# controlled notes: 1. ce2 = v ih 2. ce2 = we# = v ih figure 48. write cycle 1?we# controlled t rc t oh t a a t olz high-z t ohz t bhz t hz data valid high-z address ce1# ub#, lb# oe# data out t lz t co t ba t blz t oe t wc t wr t aw t wp high-z high-z data valid t dh data undefined t dw t ow t whz address ce1# ub#, lb# we# data in data out t cw t bw t as
february 25, 2004 psram_etrontech_06a2 16 mb psram (supplier 4) 85 preliminary notes: 1. ce2 = v ih 2. ce2 = we# = v ih figure 49. write cycle 2?cs1# controlled notes: 1. ce2 = v ih 2. ce2 = we# = v ih figure 50. write cycle3?ub#, lb# controlled t wc t aw data valid t dh t dw address ce1# ub#, lb# we# data in high-z data out t as t cw t wr t bw t wp t wc twr t aw t wp data valid t dh t dw address ce1# ub#, lb# we# data in high-z data out t cw t bw t as
86 16 mb psram (supplier 4) psram_etrontech_06a2 february 25, 2004 preliminary figure 51. deep power-down mode figure 52. power-up mode note: the s71jl064ha0 model 61 has a timing that is not supported at read operation. data will be lost if your system has multiple invalid address signal shorter than t rc during over 15 s at the read operation shown above. figure 53. abnormal timing normal operation normal operation 1 s suspend ~ ~ ~ ~ wake up deep power down mode 200 s ce2 mode ce1# ~ ~ 200 s v cc ce2 ce1# < t rc ce1# we# address > 15 s
february 25, 2004 psram_toshiba_04a2 32 mb psram (supplier 3) 87 preliminary 32 mb psram (supplier 3) 32 megabit cmos pseudo static ram features ? organized as 2,097,152 words by 16 bits ? single power supply voltage of 2.6 to 3.3 v ? direct ttl compatibility for all inputs and outputs ? deep power-down mode: memory cell data invalid ? page operation mode: ? page read operation by 8 words ? logic compatible with sram r/w (we#) pin ? standby current ?standby 70 a ? deep power-down standby 5 a ? access times: ? access time 70 ns ? ce1# access time 70 ns ? oe# access time 25 ns ? page access time 30 ns description the s71jl128hb0 contains a 33,554,432-bit, pseudo static random access mem - ory (psram) organized as 2,097,152 words by 16 bits. it provides high density, high speed, and low power. the device operates single power supply. the device also features sram-like w/r timing whereby the device is controlled by de1#, oe#, and we# on asynchronous. the device has the page access operation. page size is 8 words. the device also supports deep power-down mode, realizing low- power standby. pin description a0 to a20 = address inputs a0 to a2 = page address inputs i/o1 to i/o16 = data inputs/outputs ce1# = chip enable input ce2 = chip select input we# = write enable input oe# = output enable input lb#, ub# = data byte control inputs vdd = power gnd = ground nc = no connection
88 32 mb psram (supplier 3) psram_toshiba_04a2 february 25, 2004 preliminary operation mode note: l = low-level input (v il ), h = high-level input (v ih ), x = v ih or v il , high-z = high impedance absolute maxumum ratings note: (stresses greater than listed under "absolute maximum ratings" may cause permanent damage to the device dc characteristics note: v il (min) -1.0 v with 10 ns pulse width; vih(max) vdd+1.0 v with 10 ns pulse width mode ce1# ce2 oe# we# lb# ub# add i/o1 to i/o8 i/o9 to i/o16 power read (word) l h l h l l x d out d out i ddo read (lower byte) l h l h l h x d out high-z i ddo read (upper byte) l h l h h l x high-z d out i ddo write (word) l h x l l l x d in d in i ddo write (lower byte) l h x l l h x d in invalid i ddo write (upper byte) l h x l h l x invalid d in i ddo outputs disabled l h h h x x x high-z high-z i ddo standby h h x x x x x high-z high-z i dds deep power-down standby h l x x x x x high-z high-z i ddsd symbol rating value unit v dd power supply voltage -1.0 to 3.6 v v in input voltage -1.0 to 3.6 v v out output voltage -1.0 to 3.6 v t opr. operating temperature -40 to 85 c t strg. storage temperature -55 to 150 c p d power dissipation 0.6 w i out short circuit output current 50 ma ta b l e 1 8 . dc recommended operating conditions (t a = -40 c to 85 c) symbol pa r a m e t e r min typ. max unit v dd power supply voltage 2.6 2.75 3.3 v v ih input high voltage 2.0 - v dd + 0.3 (note) v il input low voltage -0.3 (note - 0.4
february 25, 2004 psram_toshiba_04a2 32 mb psram (supplier 3) 89 preliminary notes: 1. i ddo depends on the cycle time. 2. i ddo depends on output loading. specified values are defined with the output open condition. ac characteristics ta b l e 1 9 . dc characteristics (t a = -40 c to 85 c, vdd = 2.6 to 3.3v) symbol para mete r test condition min typ. max unit i il input leakage current v in = 0 v to v dd -1.0 - +1.0 a i lo output leakage current output disable, v out = 0 v to v dd -1.0 - +1.0 a v oh output high voltage i oh = - 0.5 ma 2.4 - - v v ol output low voltage i ol = 1.0 ma - - 0.4 v i ddo1 operating current ce1# = v il ce2 = v ih , i out = 0 ma t rc = min - - 40 ma i ddo2 page access operating current ce1# = v il , ce2 = v ih , page add. cycling, i out = 0 ma t pc = min - - 25 ma i dds standby current (mos) ce1# = v dd - 0.2 v, ce2 = v dd - 0.2 v - - 70 a i ddsd deep power-down standby current ce2 = 0.2 v - - 5 a ta b l e 2 0 . capacitance (t a = 25 c, f = 1 mhz) symbol parameter test condition max unit c in input capacitance v in = gnd 10 pf c out output capacitance v out = gnd 10 pf ta b l e 2 1 . ac characteristics and operating conditions (t a = -40 c to 85 c, v dd = 2.6 to 3.3v) symbol parameter min max unit t rc read cycle time 70 10000 ns t acc address access time ? 70 ns t co chip enable (ce#) access time ? 70 ns t oe output enable access time ? 25 ns t ba data byte control access time ? 25 ns t coe chip enable low to output active 10 ? ns t oee output enable low to output active 0 ? ns t be data byte control low to output active 0 ? ns t od chip enable high to output high-z ? 20 ns t odo output enable high to output high-z ? 20 ns t bd data byte control high to output high-z ? 20 ns t oh output data hold time 10 ? ns t pm page mode time 70 10000 ns t pc page mode cycle time 30 ? ns
90 32 mb psram (supplier 3) psram_toshiba_04a2 february 25, 2004 preliminary notes: 1. ac measurements are assumed t r , t f = 5 ns. 2. parameters t od , t odo , t bd and t odw define the time at which the output goes the open condition and are not output voltage reference levels. 3. data cannot be retained at deep power-down stand-by mode. 4. if oe# is high during the write cycle, the outputs will remain at high impedance. 5. during the output state of i/o signals, input signals of reverse polarity must not be applied. 6. if ce1# or lb#/ub# goes low coincident with or after we# goes low, the outputs will remain at high impedance. 7. if ce1# or lb#/ub# goes high coin cident with or before we# goes high, the outputs will remain at high impedance. t aa page mode address access time ? 30 ns t aoh page mode output data hold time 10 ? ns t wc write cycle time 70 10000 ns t wp write pulse width 50 ? ns t cw chip enable to end of write 70 ? ns t bw data byte control to end of write 60 ? ns t aw address valid to end of write 60 ? ns t as address set-up time 0 ? ns t wr write recovery time 0 ? ns t ceh chip enable high pulse width 10 ? ns t weh write enable high pulse width 6 ? ns t odw we# low to output high-z ? 20 ns t oew we# high to output active 0 ? ns t ds data set-up time 30 ? ns t dh data hold time 0 ? ns t cs ce2 set-up time 0 ? ns t ch ce2 hold time 300 ? s t dpd ce2 pulse width 10 ? ms t chc ce2 hold from ce1# 0 ? ns t chp ce2 hold from power on 30 ? s ta b l e 2 2 . ac test conditions parameter condition output load 30 pf + 1 ttl gate input pulse level v dd ? 0.2 v, 0.2 v timing measurements v dd 0.5 reference level v dd 0.5 t r , t f 5 ns table 21. ac characteristics and operating conditions (t a = -40 c to 85 c, v dd = 2.6 to 3.3v) (continued) symbol parameter min max unit
february 25, 2004 psram_toshiba_04a2 32 mb psram (supplier 3) 91 preliminary timing diagrams figure 54. read cycle t rc t acc addresses a0 to a20 ce#1 ce2 oe# we# lb#, ub# d out i/o1 to i/o16 t co t oh fixed high high-z high-z t oe t ba t od t odo t bd valid data out indeterminate t be t oee t coe indeterminate
92 32 mb psram (supplier 3) psram_toshiba_04a2 february 25, 2004 preliminary figure 55. page read cycle (8 words access) t pm t pc t rc t aoh fix-h hi-z hi-z ub# , lb# t be address a0 to a2 we# ce1# ce2 d out i/o1 to i/o1 address a3 to a20 t aa t aoh t aoh t pc t aa t oh t bd t od t odo t oee t ba t oe t coe t co t acc d out d out d out d out t pc t aa oe# * maximum 8 words
february 25, 2004 psram_toshiba_04a2 32 mb psram (supplier 3) 93 preliminary notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance 2. if ce1# or lb#/ub# goes low coincident with or after we# goes low, the outputs will remain at high impedance 3. during the output state of i/o signals, input signals of reverse polarity must not be applied 4. if ce1# or lb#/ub# goes high coin cident with or before we# goes high, the outputs will remain at high impedance figure 56. write cycle 1 (we# controlled) ub# , lb# t as t bw t wr valid data in t odw t wp t ds t dh t oew (see note 4) (see note 2) hi-z t cw t wc (see note 3) (see note 3) address a0 to a20 we# ce#1 ce2 d out i/o1 to i/o16 d in i/o1 to i/o16 t ch t wr t wr t aw t weh
94 32 mb psram (supplier 3) psram_toshiba_04a2 february 25, 2004 preliminary notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance 2. during the output state of i/o signals, input signals of reverse polarity must not be applied figure 57. write cycle 2 (ce# controlled) figure 58. deep power-down timing figure 59. power-on timing t wc t wp t as t cw t wr valid data in t odw t ds t dh t coe hi-z hi-z ub#, lb# t bw t be (see note 2) address a0 to a20 we# ce1# ce2 t ch d out i/o1 to i/o16 d in i/o1 to i/o16 t wr t wr t aw t ceh ce2 t cs t dpd t ch ce1# v dd ce2 t chc t chp t ch v dd min ce1#
february 25, 2004 psram_toshiba_04a2 32 mb psram (supplier 3) 95 preliminary note: if multiple invalid address cycles shorter than t rc min occur for a period greater than 10 s, at least one valid address cycle over t rc min is required during that period. figure 60. read address skew provisions note: if multiple invalid address cycles shorter than t wc min occur for a period greater than 10 s, at least one valid address cycle over t wc min, in addition to t wp min, is required during that period. figure 61. write address skew provisions we# address t rc min over 10 s ce1# we# address t wc min over 10 s ce1# t wp min
96 32 mb psram (supplier 3) psram_toshiba_04a2 february 25, 2004 preliminary
february 25, 2004 psram_toshiba_05a2 64 mb psram (supplier 3) 97 preliminary 64 mb psram (supplier 3) 64 megabit cmos pseudo static sram features ? organized as 4,194,304 words by 16 bits ? single power supply voltage of 2.6 to 3.3 v ? direct ttl compatibility for all inputs and outputs ? deep power-down mode: memory cell data invalid ? page operation mode: ? page read operation by 8 words ? logic compatible with sram r/w (we#) pin ? standby current ? standby 100 a ? deep power-down standby 5 a ? access times: ? access time 70 ns ? ce1# access time 70 ns ? oe# access time 25 ns ? page access time 30 ns description the s71jl128hc0 contains a 67,108,864-bit, pseudo static random access mem - ory (psram) organized as 4,194,304 words by 16 bits. it provides high density, high speed, and low power. the device operates on a single power supply. the device also features sram-like w/r timing whereby the device is controlled by de1#, oe#, and we# on asynchronous. the device has the page access opera - tion. page size is 8 words. the device also supports deep power-down mode, realizing low-power standby. pin description a0 to a21 = address inputs a0 to a2 = page address inputs i/o1 to i/o16 = data inputs/outputs ce1# = chip enable input ce2 = chip select input we# = write enable input oe# = output enable input lb#, ub# = data byte control inputs vdd = power gnd = ground nc = no connection
98 64 mb psram (supplier 3) psram_toshiba_05a2 february 25, 2004 preliminary operation mode note: l = low-level input (v il ), h = high-level input (v ih ), x = v ih or v il , high-z = high impedance absolute maxumum ratings note: (stresses greater than listed under "absolute maximum ratings" may cause permanent damage to the device dc characteristics note: v il (min) -1.0 v with 10 ns pulse width; vih(max) vdd+1.0 v with 10 ns pulse width mode ce1# ce2 oe# we# lb# ub# add i/o1 to i/o8 i/o9 to i/o16 power read (word) l h l h l l x d out d out i ddo read (lower byte) l h l h l h x d out high-z i ddo read (upper byte) l h l h h l x high-z d out i ddo write (word) l h x l l l x d in d in i ddo write (lower byte) l h x l l h x d in invalid i ddo write (upper byte) l h x l h l x invalid d in i ddo outputs disabled l h h h x x x high-z high-z i ddo standby h h x x x x x high-z high-z i dds deep power-down standby h l x x x x x high-z high-z i ddsd symbol rating value unit v dd power supply voltage -1.0 to 3.6 v v in input voltage -1.0 to 3.6 v v out output voltage -1.0 to 3.6 v t opr. operating temperature -25 to 85 c t strg. storage temperature -55 to 150 c p d power dissipation 0.6 w i out short circuit output current 50 ma ta b l e 2 3 . dc recommended operating conditions (t a = -25 c to 85 c) symbol pa r a m e t e r min typ. max unit v dd power supply voltage 2.6 2.75 3.3 v v ih input high voltage 2.0 - v dd + 0.3 (note) v il input low voltage -0.3 (note - 0.4
february 25, 2004 psram_toshiba_05a2 64 mb psram (supplier 3) 99 preliminary notes: 1. i ddo depends on the cycle time. 2. i ddo depends on output loading. specified values are defined with the output open condition. ac characteristics ta b l e 2 4 . dc characteristics (t a = -25 c to 85 c, vdd = 2.6 to 3.3v) symbol para mete r test condition min typ. max unit i il input leakage current v in = 0 v to v dd -1.0 - +1.0 a i lo output leakage current output disable, v out = 0 v to v dd -1.0 - +1.0 ma v oh output high voltage i oh = - 0.5 ma 2.4 - - v v ol output low voltage i ol = 1.0 ma - - 0.4 v i ddo1 operating current ce1# = v il ce2 = v ih , i out = 0 ma t rc = min - - 50 ma i ddo2 page access operating current ce1# = v il , ce2 = v ih , page add. cycling, i out = 0 ma t pc = min - - 25 ma i dds standby current (mos) ce1# = v dd - 0.2 v, ce2 = v dd - 0.2 v - - 100 a i ddsd deep power-down standby current ce2 = 0.2 v - - 5 a ta b l e 2 5 . capacitance (t a = 25 c, f = 1 mhz) symbol pa r a m e t e r test condition max unit c in input capacitance v in = gnd 10 pf c out output capacitance v out = gnd 10 pf ta b l e 2 6 . ac characteristics and operating conditions (t a = -25 c to 85 c, v dd = 2.6 to 3.3v) symbol parameter min max unit t rc read cycle time 70 10000 ns t acc address access time ? 70 ns t co chip enable (ce#) access time ? 70 ns t oe output enable access time ? 25 ns t ba data byte control access time ? 25 ns t coe chip enable low to output active 10 ? ns t oee output enable low to output active 0 ? ns t be data byte control low to output active 0 ? ns t od chip enable high to output high-z ? 20 ns t odo output enable high to output high-z ? 20 ns t bd data byte control high to output high-z ? 20 ns t oh output data hold time 10 ? ns t pm page mode time 70 10000 ns t pc page mode cycle time 30 ? ns
100 64 mb psram (supplier 3) psram_toshiba_05a2 february 25, 2004 preliminary notes: 1. ac measurements are assumed t r , t f = 5 ns. 2. parameters t od , t odo , t bd and t odw define the time at which the output goes the open condition and are not output voltage reference levels. 3. data cannot be retained at deep power-down stand-by mode. 4. if oe# is high during the write cycle, the outputs will remain at high impedance. 5. during the output state of i/o signals, input signals of reverse polarity must not be applied. 6. if ce1# or lb#/ub# goes low coincident with or after we# goes low, the outputs will remain at high impedance. 7. if ce1# or lb#/ub# goes high coin cident with or before we# goes high, the outputs will remain at high impedance. t aa page mode address access time ? 30 ns t aoh page mode output data hold time 10 ? ns t wc write cycle time 70 10000 ns t wp write pulse width 50 ? ns t cw chip enable to end of write 70 ? ns t bw data byte control to end of write 60 ? ns t aw address valid to end of write 60 ? ns t as address set-up time 0 ? ns t wr write recovery time 0 ? ns t ceh chip enable high pulse width 10 ? ns t weh write enable high pulse width 15 ? ns t odw we# low to output high-z ? 20 ns t oew we# high to output active 0 ? ns t ds data set-up time 30 ? ns t dh data hold time 0 ? ns t cs ce2 set-up time 0 ? ns t ch ce2 hold time 300 ? s t dpd ce2 pulse width 10 ? ms t chc ce2 hold from ce1# 0 ? ns t chp ce2 hold from power on 30 ? s ta b l e 2 7 . ac test conditions parameter condition output load 30 pf + 1 ttl gate input pulse level v dd ? 0.2 v, 0.2 v timing measurements v dd 0.5 reference level v dd 0.5 t r , t f 5 ns table 26. ac characteristics and operating conditions (t a = -25 c to 85 c, v dd = 2.6 to 3.3v) (continued) symbol parameter min max unit
february 25, 2004 psram_toshiba_05a2 64 mb psram (supplier 3) 101 preliminary timing diagrams figure 62. read cycle t rc t acc addresses a0 to a21 ce#1 ce2 oe# we# lb#, ub# d out i/o1 to i/o16 t co t oh fixed high high-z high-z t oe t ba t od t odo t bd valid data out indeterminate t be t oee t coe indeterminate
102 64 mb psram (supplier 3) psram_toshiba_05a2 february 25, 2004 preliminary figure 63. page read cycle (8 words access) t pm t pc t rc t aoh fix-h hi-z hi-z ub# , lb# t be address a0 to a2 we# ce1# ce2 d out i/o1 to i/o1 address a3 to a21 t aa t aoh t aoh t pc t aa t oh t bd t od t odo t oee t ba t oe t coe t co t acc d out d out d out d out t pc t aa oe# * maximum 8 words
february 25, 2004 psram_toshiba_05a2 64 mb psram (supplier 3) 103 preliminary notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance 2. if ce1# or lb#/ub# goes low coincident with or after we# goes low, the outputs will remain at high impedance 3. during the output state of i/o signals, input signals of reverse polarity must not be applied 4. if ce1# or lb#/ub# goes high coin cident with or before we# goes high, the outputs will remain at high impedance figure 64. write cycle 1 (we# controlled) ub# , lb# t as t bw t wr valid data in t odw t wp t ds t dh t oew (see note 4) (see note 2) hi-z t cw t wc (see note 3) (see note 3) address a0 to a21 we# ce#1 ce2 d out i/o1 to i/o16 d in i/o1 to i/o16 t ch t wr t wr t aw t weh
104 64 mb psram (supplier 3) psram_toshiba_05a2 february 25, 2004 preliminary notes: 1. if oe# is high during the write cycle, the outputs will remain at high impedance 2. during the output state of i/o signals, input signals of reverse polarity must not be applied figure 65. write cycle 2 (ce# controlled) figure 66. deep power-down timing figure 67. power-on timing t wc t wp t as t cw t wr valid data in t odw t ds t dh t coe hi-z hi-z ub#, lb# t bw t be (see note 2) address a0 to a21 we# ce1# ce2 t ch d out i/o1 to i/o16 d in i/o1 to i/o16 t wr t wr t aw t ceh ce2 t cs t dpd t ch ce1# v dd ce2 t chc t chp t ch v dd min ce1#
february 25, 2004 psram_toshiba_05a2 64 mb psram (supplier 3) 105 preliminary note: if multiple invalid address cycles shorter than t rc min occur for a period greater than 10 s, at least one valid address cycle over t rc min is required during that period. figure 68. read address skew provisions note: if multiple invalid address cycles shorter than t wc min occur for a period greater than 10 s, at least one valid address cycle over t wc min, in addition to t wp min, is required during that period. figure 69. write address skew provisions we# address t rc min over10 s ce1# we# address t wc min over 10 s ce1# t wp min
106 64 mb psram (supplier 3) psram_toshiba_05a2 february 25, 2004 preliminary
february 25, 2004 sram_samsung_00a2 8 mb sram (supplier 1) 107 preliminary 8 mb sram (supplier 1) 8 megabit (x8/x16) cmos sram functional description note: x = v il or v ih notes: 1. x = v il or v ih 2. address input for byte operation. ta b l e 2 8 . word mode cs1# cs#2 oe# we# byte# sa lb# ub# dq 0~7 dq 8~15 mode power h x x x x x x x high-z high-z deselected standby x l x x x x x x high-z high-z deselected standby x x x x x x h h high-z high-z deselected standby l h h h v cc x l x high-z high-z output disabled active l h h h v cc x x l high-z high-z output disabled active l h l h v cc x l h d out high-z lower byte read active l h l h v cc x h l high-z d out upper byte read active l h l h v cc x l l d out d out word read active l h x l v cc x l h d in high-z lower byte write active l h x l v cc x h l high-z d in upper byte write active l h x l v cc x l l d in d in word write active ta b l e 2 9 . byte mode cs1# cs#2 oe# we# byte# sa lb# ub# dq 0~7 dq 8~15 mode power h x x x x x x x high-z high-z deselected standby x l x x x x x x high-z high-z deselected standby l h h h v ss sa (note 2) dnu dnu high-z dnu output disabled active l h l h v ss sa (note 2) dnu dnu d out dnu lower byte read active l h x l v ss sa (note 2) dnu dnu d in dnu lower byte write active
108 8 mb sram (supplier 1) sram_samsung_00a2 february 25, 2004 preliminary absolute maximum ratings stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional operation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect reliability . dc characteristics recommended dc operating conditions notes: 1. overshoot: vcc+1.0v in case of pulse width 20ns. 2. undershoot: -1.0v in case of pulse width 20ns. 3. overshoot and undershoot are sampled, not 100% tested. capacitance (f=1mhz, t a =25 c) note: capacitance is sampled, not 100% tested item symbol ratings unit voltage on any pin relative to v ss v in ,v out -0.2 to v cc +0.3v (max. 3.6v) v voltage on v cc supply relative to v ss v cc -0.2 to 3.6v v power dissipation p d 1.0 w operating temperature t a -40 to 85 c item symbol min ty p max unit supply voltage v cc 2.7 3.0 3.3 v ground v ss 0 0 0 v input high voltage v ih 2.2 - v cc +0.2 (note 1) v input low voltage v il -0.2 (note 2) - 0.6 v item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf
february 25, 2004 sram_samsung_00a2 8 mb sram (supplier 1) 109 preliminary dc and operating characteristics item symbol test conditions min ty p max unit input leakage current i li v in =v ss to v cc -1 - 1 ma output leakage current i lo ce1#=v ih , cs2=v il or oe#=v ih or we#=v il , v io =v ss to v cc -1 - 1 ma average operating current i cc1 cycle time=1 s, 100% duty, i io =0ma, ce1# 0.2v, cs2 v cc -0.2v, byte#=v ss or v cc , v in 0.2v or v in v cc -0.2v - - 3 ma i cc2 cycle time=min, i io =0ma, 100% duty, ce1#=v il , cs2=v ih , byte#=v ss or v cc , v in =v il or v ih 70ns - - 22 ma output low voltage v ol i ol = 2.1ma - - 0.4 v output high voltage v oh i oh = -1.0ma 2.4 - v standby current (cmos) i sb1 ce1# v cc -0.2v, cs2 v cc -0.2v (ce1# controlled) or cs2 0.2v(cs2 controlled), byte3=v ss or v cc , other input =0~v cc - - 15 ma
110 8 mb sram (supplier 1) sram_samsung_00a2 february 25, 2004 preliminary ac characteristics read/write charcteristics (v cc =2.7-3.3v) data retention characteristics note: ce1# vcc-0.2v. cs2 vcc-0.2v (ce1# controlled) or cs2 0.2v (cs2 controlled), byte#=v ss or v cc parameter list symbol min max units read read cycle time t rc 70 - ns address access time t aa - 70 ns chip select to output t co1 , t co2 - 70 ns output enable to valid output t oe - 35 ns ub#, lb# access time t ba - 70 ns chip select to low-z output t lz1 , t lz2 10 - ns ub#, lb# enable to low-z output t blz 10 - ns output enable to low-z output t olz 5 - ns chip disable to high-z output t hz1 , t hz2 0 25 ns ub#, lb# disable to high-z output t bhz 0 25 ns output disable to high-z output t ohz 0 25 ns output hold from address change t oh 10 - ns write write cycle time t wc 70 - ns chip select to end of write t cw 60 - ns address set-up time t as 0 - ns address valid to end of write t aw 60 - ns ub#, lb# valid to end of write t bw 60 - ns write pulse width t wp 50 - ns write recovery time t wr 0 - ns write to output high-z t whz 0 20 ns data to write time overlap t dw 30 - ns data hold from write time t dh 0 - ns end write to output low-z t ow 5 - ns item symbol test condition min ty p max unit v cc for data retention v dr cs1# v cc -0.2v 1.5 - 3.3 v data retention current i dr v cc =3.0v, cs1# v cc -0.2v - - 15 a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - -
february 25, 2004 sram_samsung_00a2 8 mb sram (supplier 1) 111 preliminary timing diagrams figure 70. timing waveform of read cycle(1) (address controlled, cd#1=oe#=v il , cs2=we#=v ih , ub# and/or lb#=v il ) notes: 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage level s. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. figure 71. timing waveform of read cycle(2) (we#=v ih , if byte# is low, ignore ub#/lb# timing) figure 72. timing waveform of write cycle(1) (we# controlled, if byte# is low, ignore ub#/lb# timing) address data out previous data valid data valid t aa t rc t oh data valid high-z t rc address data out t oh t aa t co1 t ba t oe t olz t blz t lz t ohz t bhz t hz cs2 t co2 cs1# ub#, lb# oe# address data undefined data in data out t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow high-z high-z data valid cs2 cs1# ub#, lb# we#
112 8 mb sram (supplier 1) sram_samsung_00a2 february 25, 2004 preliminary figure 73. timing waveform of write cycle(2) (ce1# controlled, if byte# is low, ignore ub#/lb# timing) notes: 1. a write occurs during the overlap(t wp ) of low cs1# and low we#. a write begins when cs1# goes low and we# goes low with asserting ub# or lb# for single byte oper ation or simultaneously asserting ub# and lb# for double byte operation. a write ends at the earliest transition when cs1# goes high and we# goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs1# going low to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs1# or we# going high. figure 74. timing waveform of write cycle(3) (ub#, lb# controlled, byte# must be high) address data valid data in data out high-z high-z t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) t as(3) cs2 cs# ub#, lb# we# address data valid data in data out high-z high-z t wc t cw(2 ) t bw t wp(1) t dh t dw t wr(4) t aw t as(3) cs2 t cw(2) cs1# ub#, lb# we#
february 25, 2004 sram_samsung_00a2 8 mb sram (supplier 1) 113 preliminary data retention waveforms figure 75. ce1# controlled figure 76. cs2 controlled v cc 2.7v 2.2v v dr gnd data retention mode v cc - 0.2v t sdr t rdr cs1# cs1# v cc 2.7v 0.4v v dr cs2 gnd data retention mode t sdr t rdr cs2 0.2v
114 8 mb sram (supplier 1) sram_samsung_00a2 february 25, 2004 preliminary
may 25, 2004 s71jlxxxhxx_00a3 revision summary 115 preliminary trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by fasl llc. fasl llc reserves the right to change or discontinue work on any product without notice. the information in this do cument is provided as is? without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, mercha ntability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. fasl llc assumes no liability for any damages of an y kind arising out of the use of the information in this document. copyright ? 2003 fasl llc. all rights reserved. spansion, the spansion logo, mirrorbit, combinations thereof, and expressflash are trademarks of fasl llc. other company and product names used in this publication are for identification purposes only and may be trademarks of the ir respective companies. revision summary revision a (february 23, 2004) initial release. revision a+1 (february 25, 2004) global corrected supplier 4 model number to 62. revision a+2 (february 26, 2004) global corrected missed supplier 4 model number to 62. revision a+3 (may 25, 2004) s29jl064h module removed latchup characteristics.

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